- 您现在的位置：买卖IC网 > PDF目录80563 > MC68HC05C5CP (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 PDF资料下载
参数资料
| 型号： | MC68HC05C5CP |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | DIP-40 |
| 文件页数： | 25/58页 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页
Page 25
Section 4: CPU Core
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
Table 4-1: Vector Address for Interrupts and Reset
4.5.1
HARDWARE CONTROLLED INTERRUPT SEQUENCE
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts for hardware
interrupts are shown in Figure 4-4, and for STOP and WAIT in Figure 4-6. A discussion
is provided below.
1. RESET - A low input on the RESET input pin causes the program to
vector to its starting address which is specified by the contents of
memory locations $1FFE and $1FFF. The I bit in the condition code
register is also set. Much of the MCU is configured to a known state
during this type of reset as previously described in 4.4 RESETS.
2. STOP - The STOP instruction causes the oscillator to be turned off and
the processor to "sleep" until and external interrupt (IRQ) or reset
occurs.
3. WAIT - The WAIT instruction causes all processor clocks to stop, but
leaves the timer clock running. This "rest" state of the processor can be
cleared by reset, an external interrupt IRQ), or timer interrupt. There are
no special wait vectors for these individual interrupts.
4.5.2
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is executed
regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI
executes after interrupts which were pending when the SWI was fetched, but before
interrupts generated after the SWI was fetched. The interrupt service routine address is
specified by the contents of memory locations $1FFC and $1FFD.
4.5.3
EXTERNAL INTERRUPT
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and
external) are disabled. Clearing the I bit enables interrupts. The interrupt request is
latched immediately following the falling edge of IRQ. It is then synchronized internally
and serviced as specified by the contents of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger is
available as a mask option.
Register
N/A
TSR
Flag
Name
N/A
ICF
OCF
TOF
Interrupts
Reset
Software
External Interrupt
Timer Input Capture
Timer Output Compare
Timer Overflow
CPU
Interrupt
RESET
SWI
IRQ
TIMER
Vector Address
$1FFE-$1FFF
$1FFC-$1FFD
$1FFA-$1FFB
$1FF8-$1FF9
相关PDF资料 |
PDF描述 |
|---|---|
| MB89475PFV | 8-BIT, 12.5 MHz, MICROCONTROLLER, PQFP48 |
| MAH28151FXXXX | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, CQFP68 |
| MPC8245LZU300D | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| MPC8250AZUMHBB | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480 |
| MPC859DSLZP66 | 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05C8 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PROGRAMMING REFRERENCE GUIDE |
| MC68HC05C8A | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Microcontrollers |
| MC68HC05C8ACFN | 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 44 Pin, Plastic, PLCC |
| MC68HC05C9 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:TECHNICAL DATA |
| MC68HC05C9A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
发布紧急采购，3分钟左右您将得到回复。