参数资料
型号: MC68HC11F1VPU2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: Technical Summary 8-Bit Microcontroller
中文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-80
文件页数: 92/163页
文件大小: 711K
代理商: MC68HC11F1VPU2
MOTOROLA
CENTRAL PROCESSING UNIT
MC68HC11F1
3-10
TECHNICAL DATA
BGT (rel)
Branch if >
Zero
? Z + (N
⊕ V) = 0
REL
2E
rr
3
————————
BHI (rel)
Branch if
Higher
? C + Z = 0
REL
22
rr
3
————————
BHS (rel)
Branch if
Higher or
Same
? C = 0
REL
24
rr
3
————————
BITA (opr)
Bit(s) Test A
with Memory
A M
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
85
95
B5
A5
18
A5
ii
dd
hh ll
ff
2
3
4
5
————
0—
BITB (opr)
Bit(s) Test B
with Memory
B M
B
IMM
B
DIR
B
EXT
B
IND,X
B
IND,Y
C5
D5
F5
E5
18
E5
ii
dd
hh ll
ff
2
3
4
5
————
0—
BLE (rel)
Branch if
Zero
? Z + (N
⊕ V) = 1
REL
2F
rr
3
————————
BLO (rel)
Branch if
Lower
? C = 1
REL
25
rr
3
————————
BLS (rel)
Branch if
Lower or
Same
? C + Z = 1
REL
23
rr
3
————————
BLT (rel)
Branch if <
Zero
? N
⊕ V = 1
REL
2D
rr
3
————————
BMI (rel)
Branch if
Minus
? N = 1
REL
2B
rr
3
————————
BNE (rel)
Branch if not =
Zero
? Z = 0
REL
26
rr
3
————————
BPL (rel)
Branch if Plus
? N = 0
REL
2A
rr
3
————————
BRA (rel)
Branch Always
? 1 = 1
REL
20
rr
3
————————
BRCLR(opr)
(msk)
(rel)
Branch if
Bit(s) Clear
? M mm = 0
DIR
IND,X
IND,Y
13
1F
18
1F
dd mm rr
ff mm rr
6
7
8
————————
BRN (rel)
Branch Never
? 1 = 0
REL
21
rr
3
————————
BRSET(opr)
(msk)
(rel)
Branch if Bit(s)
Set
? (M) mm = 0
DIR
IND,X
IND,Y
12
1E
18
1E
dd mm rr
ff mm rr
6
7
8
————————
BSET (opr)
(msk)
Set Bit(s)
M + mm
M
DIR
IND,X
IND,Y
14
1C
18
1C
dd mm
ff mm
6
7
8
————
0—
BSR (rel)
Branch to
Subroutine
See Figure 3–2
REL
8D
rr
6
————————
BVC (rel)
Branch if
Overflow Clear
? V = 0
REL
28
rr
3
————————
BVS (rel)
Branch if
Overflow Set
? V = 1
REL
29
rr
3
————————
CBA
Compare A to
B
A – B
INH
11
2
————
CLC
Clear Carry Bit
0
C
INH
0C
2
———————
0
CLI
Clear Interrupt
Mask
0
I
INH
0E
2
———
0
————
CLR (opr)
Clear Memory
Byte
0
M
EXT
IND,X
IND,Y
7F
6F
18
6F
hh ll
ff
6
7
————
0100
CLRA
Clear
Accumulator A
0
A
A
INH
4F
2
————
0100
CLRB
Clear
Accumulator B
0
B
B
INH
5F
2
————
0100
CLV
Clear Overflow
Flag
0
V
INH
0A
2
——————
0
CMPA (opr)
Compare A to
Memory
A – M
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
81
91
B1
A1
18
A1
ii
dd
hh ll
ff
2
3
4
5
————
CMPB (opr)
Compare B to
Memory
B – M
B
IMM
B
DIR
B
EXT
B
IND,X
B
IND,Y
C1
D1
F1
E1
18
E1
ii
dd
hh ll
ff
2
3
4
5
————
Table 3-2 Instruction Set (Sheet 2 of 6)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
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