参数资料
型号: MC68HC11F1VPU2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: Technical Summary 8-Bit Microcontroller
中文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-80
文件页数: 95/163页
文件大小: 711K
代理商: MC68HC11F1VPU2
MC68HC11F1
CENTRAL PROCESSING UNIT
MOTOROLA
TECHNICAL DATA
3-13
NOP
No operation
No Operation
INH
01
2
————————
ORAA (opr)
OR
Accumulator
A (Inclusive)
A + M
A
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
8A
9A
BA
AA
18
AA
ii
dd
hh ll
ff
2
3
4
5
————
0—
ORAB (opr)
OR
Accumulator
B (Inclusive)
B + M
B
B
IMM
B
DIR
B
EXT
B
IND,X
B
IND,Y
CA
DA
FA
EA
18
EA
ii
dd
hh ll
ff
2
3
4
5
————
0—
PSHA
Push A onto
Stack
A
Stk,SP = SP – 1 A
INH
36
3
————————
PSHB
Push B onto
Stack
B
Stk,SP = SP – 1 B
INH
37
3
————————
PSHX
Push X onto
Stack (Lo
First)
IX
Stk,SP = SP – 2
INH
3C
4
————————
PSHY
Push Y onto
Stack (Lo
First)
IY
Stk,SP = SP – 2
INH
18
3C
5
————————
PULA
Pull A from
Stack
SP = SP + 1, A
Stk A
INH
32
4
————————
PULB
Pull B from
Stack
SP = SP + 1, B
Stk B
INH
33
4
————————
PULX
Pull X From
Stack (Hi
First)
SP = SP + 2, IX
Stk
INH
38
5
————————
PULY
Pull Y from
Stack (Hi
First)
SP = SP + 2, IY
Stk
INH
18
38
6
————————
ROL (opr)
Rotate Left
EXT
IND,X
IND,Y
79
69
18
69
hh ll
ff
6
7
————
ROLA
Rotate Left A
A
INH
49
2
————
ROLB
Rotate Left B
B
INH
59
2
————
ROR (opr)
Rotate Right
EXT
IND,X
IND,Y
76
66
18
66
hh ll
ff
6
7
————
RORA
Rotate Right A
A
INH
46
2
————
RORB
Rotate Right B
B
INH
56
2
————
RTI
Return from
Interrupt
See Figure 3–2
INH
3B
12
RTS
Return from
Subroutine
See Figure 3–2
INH
39
5
————————
SBA
Subtract B
from A
A – B
A
INH
10
2
————
SBCA (opr)
Subtract with
Carry from A
A – M – C
A
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
82
92
B2
A2
18
A2
ii
dd
hh ll
ff
2
3
4
5
————
SBCB (opr)
Subtract with
Carry from B
B – M – C
B
B
IMM
B
DIR
B
EXT
B
IND,X
B
IND,Y
C2
D2
F2
E2
18
E2
ii
dd
hh ll
ff
2
3
4
5
————
SEC
Set Carry
1
C
INH
0D
2
———————
1
SEI
Set Interrupt
Mask
1
I
INH
0F
2
———
1
————
SEV
Set Overflow
Flag
1
V
INH
0B
2
——————
1
STAA (opr)
Store
Accumulator
A
M
A
DIR
A
EXT
A
IND,X
A
IND,Y
97
B7
A7
18
A7
dd
hh ll
ff
3
4
5
————
0—
Table 3-2 Instruction Set (Sheet 5 of 6)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
C
b7
b0
C
b7
b0
C
b7
b0
C
b7
b0
C
b7
b0
C
b7
b0
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