参数资料
型号: MC68HC11F1VPU2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: Technical Summary 8-Bit Microcontroller
中文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-80
文件页数: 94/163页
文件大小: 711K
代理商: MC68HC11F1VPU2
MOTOROLA
CENTRAL PROCESSING UNIT
MC68HC11F1
3-12
TECHNICAL DATA
INY
Increment
Index Register
Y
IY + 1
IY
INH
18
08
4
—————
——
JMP (opr)
Jump
See Figure 3–2
EXT
IND,X
IND,Y
7E
6E
18
6E
hh ll
ff
3
4
————————
JSR (opr)
Jump to
Subroutine
See Figure 3–2
DIR
EXT
IND,X
IND,Y
9D
BD
AD
18
AD
dd
hh ll
ff
5
6
7
————————
LDAA (opr)
Load
Accumulator
A
M
A
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
86
96
B6
A6
18
A6
ii
dd
hh ll
ff
2
3
4
5
————
0—
LDAB (opr)
Load
Accumulator
B
M
B
B
IMM
B
DIR
B
EXT
B
IND,X
B
IND,Y
C6
D6
F6
E6
18
E6
ii
dd
hh ll
ff
2
3
4
5
————
0—
LDD (opr)
Load Double
Accumulator
D
M
A,M + 1 B
IMM
DIR
EXT
IND,X
IND,Y
CC
DC
FC
EC
18
EC
jj kk
dd
hh ll
ff
3
4
5
6
————
0—
LDS (opr)
Load Stack
Pointer
M : M + 1
SP
IMM
DIR
EXT
IND,X
IND,Y
8E
9E
BE
AE
18
AE
jj kk
dd
hh ll
ff
3
4
5
6
————
0—
LDX (opr)
Load Index
Register
X
M : M + 1
IX
IMM
DIR
EXT
IND,X
IND,Y
CE
DE
FE
EE
CD
EE
jj kk
dd
hh ll
ff
3
4
5
6
————
0—
LDY (opr)
Load Index
Register
Y
M : M + 1
IY
IMM
DIR
EXT
IND,X
IND,Y
18
CE
18
DE
18
FE
1A
EE
18
EE
jj kk
dd
hh ll
ff
4
5
6
————
0—
LSL (opr)
Logical Shift
Left
EXT
IND,X
IND,Y
78
68
18
68
hh ll
ff
6
7
————
LSLA
Logical Shift
Left A
A
INH
48
2
————
LSLB
Logical Shift
Left B
B
INH
58
2
————
LSLD
Logical Shift
Left Double
INH
05
3
————
LSR (opr)
Logical Shift
Right
EXT
IND,X
IND,Y
74
64
18
64
hh ll
ff
6
7
————
0
LSRA
Logical Shift
Right A
A
INH
44
2
————
0
LSRB
Logical Shift
Right B
B
INH
54
2
————
0
LSRD
Logical Shift
Right Double
INH
04
3
————
0
MUL
Multiply 8 by 8
A
B D
INH
3D
10
———————
NEG (opr)
Two’s
Complement
Memory Byte
0 – M
M
EXT
IND,X
IND,Y
70
60
18
60
hh ll
ff
6
7
————
NEGA
Two’s
Complement
A
0 – A
A
A
INH
40
2
————
NEGB
Two’s
Complement
B
0 – B
B
B
INH
50
2
————
Table 3-2 Instruction Set (Sheet 4 of 6)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
A
B
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
A
B
b7
b0
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