参数资料
型号: ML60851DTB
厂商: LAPIS SEMICONDUCTOR CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件页数: 51/84页
文件大小: 394K
代理商: ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
54/83
DMA Transfer Timing (2)
ML60851D to Memory (Single Transfer, Dual Address Mode)
Parameter
Symbol
Condition
Min.
Max.
Unit
Note
DREQ Disable Time
t
1
Load 20 pF
20
ns
DREQ Enable Time
t
2
—63
ns
4
Read Data Delay Time
t
3
Load 20 pF
25
ns
1
Data Hold Time
t
4
Load 20 pF
0
25
ns
8-bit DMA
63
ns
2
Recovery Time
t
5
16-bit DMA
105
ns
3
Notes: 1. When in Dual Address mode, the DACK is ignored.
t
1 and t3 are defined depending on CS or RD which becomes active last.
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns)
3. 5-clock time of oscillation clock (clock period: 21 ns)
4. It is possible to increase t
2 by setting the DMA interval register (DMAINTVL).
A7:A0
DREQ
t
1
t
3
t
2
t
5
t
4
CS
RD
DOUT
DATA OUT
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