参数资料
型号: ML60851DTB
厂商: LAPIS SEMICONDUCTOR CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件页数: 84/84页
文件大小: 394K
代理商: ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
8/83
End Point 2 Receive FIFO (EP2RXFIFO)
Read address
42h
Write address
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×××
××××
×
After a bus reset
×××
××××
×
Definition
EP2 Receive data (R)
It is possible to read out the EP2 receive data by reading the address 42h. When EP2 is set for bulk reception (Bulk
OUT), the local MCU should read EP2RXFIFO when the ML60851D issues an EP2 packet ready interrupt request.
It is possible to read successively the data in the packet by reading continuously. When the data transfer direction
of EP2 is set as ‘Transmit’, all accesses to this address will be invalid.
The EP2RXFIFO is cleared under the following conditions:
1. When an OUT token is received for EP2.
2. When the EP2 receive packet ready bit is reset. (A “1” is written in PKTRDY(2).)
3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).
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