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参数资料
| 型号： | MM908E630CVFC |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, QCC44 |
| 封装： | 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44 |
| 文件页数： | 14/48页 |
| 文件大小： | 2299K |
| 代理商： | MM908E630CVFC |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
21
908E630
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
ADC SUPPLY PINS (VDDA AND VSSA)
VDDA and VSSA are the power supply pins for the analog-
to-digital converter (ADC). It is recommended that a high-
quality ceramic decoupling capacitor be placed between
these Pins.
For details refer to the 68HC908EY16 datasheet.
ADC REFERENCE PINS (VREFL AND VREFH)
VREFL and VREFH are the reference voltage pins for the
ADC. It is recommended that a high quality ceramic
decoupling capacitor be placed between these pins.
For details refer to the 68HC908EY16 datasheet.
POWER SUPPLY PINS (VS1 AND VS2)
Those are the battery level voltage supply pins. In
application VS1 and VS2 pins must be protected against
reverse battery connection and negative transient voltages
with external components.
The high side switches (HS1 and HS2) are supplied by the
VS2 pin, all other internal blocks of the analog die are
supplied by VS1 pin.
+5.0 V MAIN REGULATOR OUTPUT PIN (VDD)
The VDD pin is needed to place an external capacitor to
stabilize the regulated output voltage. The VDD pin is
intended to supply the embedded microcontroller. The pin is
current limited against shorts to GND and over-temperature
protected.
During Stop mode the voltage regulator does not operate
with its full capabilities and the output current is limited.
During Sleep mode the regulator output is completely shut
down.
Note: VDD, VREFH/VDDA and EVDD pins must be
connected together.
VOLTAGE REGULATOR AND CURRENT SENSE
GROUND PIN (AGND)
The AGND pin is the ground pin of the voltage regulator
and the current sense module.
Note: PGND, LGND, AGND and VREFL/VSSA/EVSS pins
must be connected together.
HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)
Provides a switchable supply for external hall sensors.
While in Normal mode, this current limited output can be
controlled through the SPI.
The HVDD pin is needed to place an external capacitor to
stabilize the regulated output voltage.
LOW SIDE OUTPUT PINS (LS1 AND LS2)
LS1 and LS2 are the low side driver outputs. Those
outputs are short-circuit protected and include active clamp
circuitry to drive inductive loads. The switches are controlled
through the SPI and can be configured to respond to a signal
applied to the PWMIN input of the analog die which is
internally connected to the PTD0/TACH0 output of the MCU
die.
Both low side switches are protected against overheating.
HIGH SIDE OUTPUT PINS (HS1 AND HS2)
HS1 and HS2 switch structures connected to the VS2
supply pin. They are short-circuit protected, both outputs are
also protected against overheating.
HS1 and HS2 are controlled by SPI and can respond to a
signal applied to the PWMIN input of the analog die which is
internally connected to the PTD0/TACH0 output of the MCU
die.
HS1 and HS2 outputs can also be used during low-power
mode for the cyclic-sense of the wake inputs.
VOLTAGE SENSE PIN (VSENSE)
This input can be connected directly to the battery line. It
is protected against battery reverse connection. The voltage
present in this input is scaled down by an internal voltage
divider and can be routed to the ADOUT0 output of the
analog die.
DIGITAL/ANALOG INPUT PINS (L1, L2, L3 AND L4)
Lx pins are multi purpose inputs. They can be used as
digital inputs, which can be sampled by reading the SPI and
used for wake-up when in low power mode, or used as
analog inputs for the analog multiplexer.
When used as wake-up inputs, L1-L4 can be configured to
operate in cyclic-sense mode. In this mode, one of the high
side switches is configured to be periodically turned on and
sample the wake-up inputs. If a state change is detected
between two cycles, a wake-up is initiated.
When used as analog input, the voltage present on the Lx
Pins is scaled down by an internal voltage divider and can
routed to the ADOUT0 output of the analog die through the
analog multiplexer.
Note: If a Lx input is selected in the analog multiplexer, it
will be disabled as digital input and remains disabled in low
power mode. No wake-up can be sensed in that condition.
When an Lx input is not selected in the analog multiplexer,
the voltage divider is disconnected from that input.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems, and is
compliant to the LIN bus specification 2.0, 2.1, and SAE
J2602-2. The LIN interface is only active during Normal and
Normal Request modes.
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