参数资料
型号: MM908E630CVFC
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROCONTROLLER, QCC44
封装: 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44
文件页数: 7/48页
文件大小: 2299K
代理商: MM908E630CVFC
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
908E630
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
LIN Physical Layer - Driver Characteristics for Normal Slew Rate - 20.0 kBit/sec(47),(48)
Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 X tBIT)
THREC(MAX) = 0.744 X VSUP; THDOM(MAX) = 0.581 X VSUP
7.0 V
VSUP 18 V, tBIT = 50 s
D1
0.396
Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT)
THREC(MIN) = 0.284 x VSUP; THDOM(MIN) = 0.422 x VSUP
7.6 V
VSUP 18 V, tBIT = 50 s
D2
0.581
LIN Physical Layer - Driver Characteristics for Slow Slew Rate - 10.4 kBit/sec(47),(48)
Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT)
THREC(MAX) = 0.778 x VSUP; THDOM(MAX) = 0.616 x VSUP
7.0 V
VSUP 18 V, tBIT = 96 s
D3
0.417
Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT)
THREC(MIN) = 0.251 x VSUP; THDOM(MIN) = 0.389 x VSUP
7.6 V
VSUP 18 V, tBIT = 96 s
D4
0.590
LIN PHYSICAL LAYER - DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SRFAST
20
V/
μs
LIN PHYSICAL LAYER - RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS(47)
Propagation Delay of Receiver, tREC_PD=max (tREC_PDR, tREC_PDF)(49)
tRX_PD
4.2
6.0
μs
Symmetry of Receiver Propagation Delay; tREC_PDF - tREC_PDR(49)
tRX_SYM
-2.0
2.0
μs
Bus Wake-up Deglitcher (Sleep and Stop Modes)(50)
tPROPWL
42
70
95
μs
Bus Wake-up Event Reported
From Sleep Mode(51)
From Stop Mode(52)
tWAKE
9.0
27
1500
35
μs
TxD Permanent Dominant State Delay
tTXDDOM
0.65
1.0
1.35
s
Notes
47.
VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TxD
signal to LIN signal threshold defined at each parameter. See Figure 6, page 17.
48.
49.
50.
See Figure 9, page 18 for Sleep and Figure 10, page 18 for Stop mode.
51.
The measurement is done with 1.0 F capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V.
See Figure 9, page 18. The delay depends of the load and capacitor on VDD.
52.
In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 10,
Table 4. Dynamic Electrical Characteristics (continued)
All characteristics are for the analog die only. Refer to the 68HC908EY16A datasheet for characteristics of the microcontroller
die. Characteristics noted under conditions 5.5 V
≤ VSUP ≤ 18 V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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