参数资料
型号: MM908E630CVFC
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROCONTROLLER, QCC44
封装: 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44
文件页数: 26/48页
文件大小: 2299K
代理商: MM908E630CVFC
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
908E630
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 17. SPI Protocol
During the inactive phase of the CS (HIGH), the new data
transfer is prepared.
The falling edge of the CS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
With the rising edge of the SPI clock, SCLK the data is
moved to MISO/MOSI pins. With the falling edge of the SPI
clock SCLK the data is sampled by the Receiver.
The data transfer is only valid if exactly 8 sample clock
edges are present in the active (low) phase of CS.
The rising edge of the slave select CS indicates the end of
the transfer and latches the write data (MOSI) into the
register. The CS high forces MISO to the high-impedance
state.
Registers reset value is described along with the reset
condition. Reset condition is the condition causing the bit to
be set at the reset value. The main reset conditions are:
- Power-on Reset (POR): level at which the logic is reset
and BATFAIL flag sets.
- Reset mode
- Reset done by the RST_A pin (ext_reset)
A3
A2
A1
A0
C3
C2
C1
C0
LIN S
HSS
LSS
S3
S2
S1
S0
R egister w rite data
R egister read data
R ising edge of SPS C K
C hange M ISO/M O S I O utput
Falling edge of SPS C K
Sample MISO/M O SI Input
W rite data latch
CS
MOSI
MISO
SCLK
R ead data latch
VM S
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