Analog Integrated Circuit Device Data
Freescale Semiconductor
27
908E630
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
From Sleep mode, the following wake-up events can be
configured:
Wake-up from Lx inputs without cyclic sense
Cyclic sense wake-up inputs
Force wake-up
LIN wake-up
WINDOW WATCHDOG
The 908E630 analog die includes a configurable window
watchdog which is active in Normal mode. The watchdog can
be configured by an external resistor connected to the
WDCONF pin. The resistor is used to achieve higher
precision in the time-base used for the watchdog.
SPI clears are performed by writing through the SPI in the
MOD bits of the SPI - Mode Control register (MCR).
During the first half of the SPI timeout, watchdog clears are
not allowed after the first half the window for the clear
operation opens. If a clear operation is performed outside the
window the 908E630 analog die will reset the MCU, in the
same way as when the watchdog overflows.
Figure 13. Window Watchdog Operation
To disable the watchdog function in Normal mode, the
user must connect the WDCONF pin to ground. This
measure effectively disables Normal-Request mode. The
WDOFF bit in WSR register will be set. This condition is only
detected during Reset mode.
If neither a resistor nor a connection to ground are
detected, the watchdog falls back to the internal lower
precision time-base of 150 ms (typ.) and signals the faulty
condition through the SPI - Watchdog Status Register
(WSR).
The watchdog time-base can be further divided by a
prescaler which can be configured by the SPI - Timing
Control Register (TCR). During Normal Request mode, the
windowing watchdog is not active but there is a 150 ms (typ.)
timeout for leaving the Normal Request mode. In case of a
timeout, the 908E630 analog die will enter into reset mode,
resetting the microcontroller before entering again into
Normal-Request mode.
HIGH SIDE OUTPUT PINS HS1 AND HS2
These outputs are two high side drivers intended to drive
small resistive load or LEDs incorporating the following
features:
PWM capability up to 10 kHz (software maskable)
open load detection
current limitation
over-temperature shutdown (with maskable interrupt)
high voltage shutdown (software maskable)
cyclic sense
The high side switches are controlled by the bits HS1:2 in
the High Side Control Register.
PWM capability (direct access)
Each high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If both the bits HS1 and PWMHS1 are set in the High Side
Control Register, then the HS1 driver is turned on if the
PWMIN pin is high, and turned of if the PWMIN pin is low.
The same applies to the HS2 and PWMHS2 bits for the
HS2 driver.
Window closed
no watchdog clear allowed
Window open
for watchdog clear
WD timing x 50%
WD period (PWD)
WD timing selected by resistor on WDCONF terminal.
(tPWD)