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参数资料
| 型号： | MM908E630CVFC |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, QCC44 |
| 封装： | 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44 |
| 文件页数： | 25/48页 |
| 文件大小： | 2299K |
| 代理商： | MM908E630CVFC |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
31
908E630
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
If the bit LINM is set in the Interrupt Mask Register, an
Interrupt IRQ_A will be generated.
The transmitter is automatically re-enabled once the
condition is gone (transition on RxD) and TxD is High.
A read of the LIN Status Register without the RxD pin
short-circuit condition will clear the bit RXSHORT.
TXD dominant detection (LIN Interrupt)
The LIN transceiver monitors the TxD input pin to detect
stuck in dominant (0 V) condition. In case of a stuck condition
(TXD pin 0 V for more than 1 second (typ.), the transmitter is
shut down and the bit TXDOM in the LIN Status Register is
set.
If the bit LINM is set in the Interrupt Mask Register an
Interrupt IRQ_A will be generated.
The transmitter is automatically re-enabled once TxD is
High.
A read of the LIN Status Register with the TxD pin at 5.0 V
will clear the bit TXDOM.
LIN Receiver Operation Only
While in normal mode the activation of the RXONLY bit
disables the LIN TX driver. In the case of a LIN error condition
this bit is automatically set. In case a low power mode is
selected with this bit set, the LIN wake-up functionality is
disabled. Then in STOP mode, the Rx pin will reflect the state
of the LIN bus.
STOP Mode and Wake-up Feature
During Stop mode operation, the transmitter of the
physical layer is disabled. The receiver is still active and able
to detect wake-up events on the LIN bus line. A dominant
level longer than tPROPWL followed by a rising edge will
generate a wake-up interrupt, and will be reported in the
SLEEP Mode and Wake-up Feature
During Sleep mode operation, the transmitter of the
physical layer is disabled. The receiver must be active to
detect wake-up events on the LIN bus line. A dominant level
longer than tPROPWL followed by a rising edge, will generate
a system wake-up (Reset), and will be reported in the
Interrupt Source Register (ISR). See Figure 9, page 18.
LOGIC COMMANDS AND REGISTERS
908E630 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between a microcontroller (master) and the 908E630
analog die (slave).
The interface consists of four pins (see Figure 17):
CS—Chip Select
MOSI—Master-out Slave-in
MISO—Master-in Slave-out
SCLK—Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
status bits (VMS,LINS,HSS,LSS) + 4 bits of status
information (S3:S0).
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