参数资料
型号: MPC603E
厂商: Motorola, Inc.
英文描述: PowerPC 603e RISC Microprocessor
中文描述: RISC微处理器的PowerPC 603e
文件页数: 10/31页
文件大小: 132K
代理商: MPC603E
10
PowerPC 603e RISC Microprocessor Technical Summary
1.7.1 Power Management
The 603e provides four power modes selectable by setting the appropriate control bits in the machine state
register (MSR) and hardware implementation register 0 (HID0) registers. The four power modes are as
follows:
Full-power–This is the default power state of the 603e. The 603e is fully powered and the internal
functional units are operating at the full processor clock speed. If the dynamic power management
mode is enabled, functional units that are idle will automatically enter a low-power state without
affecting performance, software execution, or external hardware.
Doze–All the functional units of the 603e are disabled except for the time base/decrementer
registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous
interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine
check brings the 603e into the full-power state. The 603e in doze mode maintains the PLL in a fully
powered state and locked to the system external clock input (SYSCLK) so a transition to the full-
power state takes only a few processor clock cycles.
Nap–The nap mode further reduces power consumption by disabling bus snooping, leaving only the
time base register and the PLL in a powered state. The 603e returns to the full-power state upon
receipt of an external asynchronous interrupt, a system management interrupt, a decrementer
exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state from
a nap state takes only a few processor clock cycles.
Sleep–Sleep mode reduces power consumption to a minimum by disabling all internal functional
units, after which external system logic may disable the PLL and SYSCLK. Returning the 603e to
the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an
external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine
check input (MCP) signal after the time required to relock the PLL.
1.7.2 Time Base/Decrementer
The time base is a 64-bit register (accessed as two 32-bit registers) that is incremented once every four bus
clock cycles; external control of the time base is provided through the time base enable (TBEN) signal. The
decrementer is a 32-bit register that can generate a maskable decrementer exception after a programmable
delay. The contents of the decrementer register are decremented once every four bus clock cycles, and the
decrementer exception is generated as the count passes through zero.
1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface
The 603e provides IEEE 1149.1 and COP functions for facilitating board testing and chip debug. The IEEE
1149.1 test interface provides a means for boundary-scan testing the 603e and the board to which it is
attached. The COP function shares the IEEE 1149.1 test port, provides a means for executing test routines,
and facilitates chip and software debugging.
1.7.4 Clock Multiplier
The internal clocking of the 603e is generated from and synchronized to the external clock signal, SYSCLK,
by means of a voltage-controlled oscillator-based PLL. The PLL provides programmable internal processor
clock rates of 1x, 1.5x, 2x, 2.5x, 3x, 3.5x, and 4x multiples of the externally supplied clock frequency for
the PID6-603e, and multiples of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, and 6x of the externally provided
clock for the PID7v-603e. The bus clock is the same frequency and is synchronous with SYSCLK. The
configuration of the PLL can be read by software from hardware implementation register 1 (HID1).
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