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参数资料
| 型号： | MPC603E |
| 厂商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微处理器的PowerPC 603e |
| 文件页数： | 12/31页 |
| 文件大小： | 132K |
| 代理商： | MPC603E |
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PowerPC 603e RISC Microprocessor Technical Summary
PowerPC virtual environment architecture (VEA)—Describes the memory model for a
multiprocessor environment, defines cache control instructions, and describes other aspects of
virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may
not necessarily adhere to the OEA.
PowerPC operating environment architecture (OEA)—Defines the memory management model,
supervisor-level registers, synchronization requirements, and the exception model.
Implementations that conform to the OEA also adhere to the UISA and the VEA.
The PowerPC architecture allows a wide range of designs for such features as cache and system interface
implementations. The 603e implementations support the three levels of the architecture described above.
For more information about the PowerPC architecture, see
Programming Environments
user’s manual.
PowerPC Microprocessor Family: The
Specific features of the 603e are listed in Section 1.1, “PowerPC 603e Microprocessor Features.”
2.2 PowerPC Registers and Programming Model
The PowerPC architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are provided as immediate values
embedded in the instruction opcode. The three-register instruction format allows specification of a target
register distinct from the two source operands. Load and store instructions transfer data between registers
and memory.
PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the
operating system) and user mode of operation (used by the application software). The programming models
incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers. Each
PowerPC microprocessor also has its own unique set of hardware implementation (HID) registers.
Having access to privileged instructions, registers, and other resources allows the operating system to
control the application environment (providing virtual memory and protecting operating-system and critical
machine resources). Instructions that control the state of the processor, the address translation mechanism,
and supervisor registers can be executed only when the processor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603e.
2.2.1 General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These registers are 32
bits wide in 32-bit PowerPC microprocessors and 64 bits wide in 64-bit PowerPC microprocessors. The
GPRs serve as the data source or destination for all integer instructions.
2.2.2 Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers (FPRs). The FPRs serve
as the data source or destination for floating-point instructions. These registers can contain data objects of
either single- or double-precision floating-point formats.
2.2.3 Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of certain
operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and
provide a mechanism for testing and branching.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC603E7TEC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| MPC603E7TED | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| mpc603efe100ln | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MPC603EFE100TN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Specifications |
| MPC603EFE133LN | 制造商:Motorola Inc 功能描述: |
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