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PowerPC 603e RISC Microprocessor Technical Summary
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2.2.4 Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains all exception
signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance
with the IEEE-754 standard.
2.2.5 Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the processor. The
contents of this register are saved when an exception is taken and restored when the exception handling
completes. The 603e implements the MSR as a 32-bit register; 64-bit PowerPC processors implement a 64-
bit MSR.
2.2.6 Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers
(SRs). To speed access, the 603e implements the segment registers as two arrays; a main array (for data
memory accesses) and a shadow array (for instruction memory accesses). Loading a segment entry with the
Move to Segment Register
(
mtsr
)
instruction loads both arrays.
2.2.7 Special-Purpose Registers (SPRs)
The PowerPC operating environment architecture defines numerous special-purpose registers that serve a
variety of functions, such as providing controls, indicating status, configuring the processor, and performing
special operations. During normal execution, a program can access the registers, shown in Figure 2,
depending on the program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit
in the MSR). Note that registers such as the GPRs and FPRs are accessed through operands that are part of
the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that
purpose such as Move to Special-Purpose Register (
(
mfspr
) instructions) or implicit, as the part of the execution of an instruction. Some registers are accessed
both explicitly and implicitly
mtspr
) and Move from Special-Purpose Register
In the 603e, all SPRs are 32 bits wide.
2.2.7.1 User-Level SPRs
The following 603e SPRs are accessible by user-level software:
Link register (LR)—The link register can be used to provide the branch target address and to hold
the return address after branch and link instructions. The LR is 32 bits wide in 32-bit
implementations.
Count register (CTR)—The CTR is decremented and tested automatically as a result of branch-and-
count instructions. The CTR is 32 bits wide in 32-bit implementations.
XER register—The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit,
and a field specifying the number of bytes to be transferred by a Load String Word Indexed (
or Store String Word Indexed (
stswx
) instruction.
lswx
)
2.2.7.2 Supervisor-Level SPRs
The 603e also contains SPRs that can be accessed only by supervisor-level software. These registers consist
of the following:
The 32-bit DSISR defines the cause of data access and alignment exceptions.
The data address register (DAR) is a 32-bit register that holds the address of an access after an
alignment or DSI exception.