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参数资料
| 型号： | MPC603E |
| 厂商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微处理器的PowerPC 603e |
| 文件页数： | 14/31页 |
| 文件大小： | 132K |
| 代理商： | MPC603E |
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14
PowerPC 603e RISC Microprocessor Technical Summary
Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for
causing a decrementer exception after a programmable delay.
The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for
pages. (Note that physical address is referred to as real address in the architecture specification.)
The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 603e for
saving the address of the instruction that caused the exception, and the address to return to when a
Return from Interrupt (
rfi
) instruction is executed.
The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status
on exceptions and to restore machine status when an
The 32-bit SPRG0–SPRG3 registers are provided for operating system use.
The external access register (EAR) is a 32-bit register that controls access to the external control
facility through the External Control In Word Indexed (
Indexed (
ecowx
) instructions.
The time base register (TB) is a 64-bit register that maintains the time of day and operates interval
timers. The TB consists of two 32-bit fields—time base upper (TBU) and time base lower (TBL).
The processor version register (PVR) is a 32-bit, read-only register that identifies the version
(model) and revision level of the PowerPC processor.
Block address translation (BAT) arrays—The PowerPC architecture defines 16 BAT registers,
divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs). See
Figure 2 for a list of the SPR numbers for the BAT arrays.
rfi
instruction is executed.
eciwx
) and External Control Out Word
The following supervisor-level SPRs are implementation-specific to the 603e:
The DMISS and IMISS registers are read-only registers that are loaded automatically upon an
instruction or data TLB miss.
The HASH1 and HASH2 registers contain the physical addresses of the primary and secondary
page table entry groups (PTEGs).
The ICMP and DCMP registers contain a duplicate of the first word in the page table entry (PTE)
for which the table search is looking.
The required physical address (RPA) register is loaded by the processor with the second word of the
correct PTE during a page table search.
The hardware implementation (HID0 and HID1) registers provide the means for enabling the
603e’s checkstops and features, and allows software to read the configuration of the PLL
configuration signals.
The instruction address breakpoint register (IABR) is loaded with an instruction address that is
compared to instruction addresses in the dispatch queue. When an address match occurs, an
instruction address breakpoint exception is generated.
Figure 2 shows all the 603e registers available at the user and supervisor level. The numbers to the right of
the SPRs indicate the number that is used in the syntax of the instruction operands to access the register.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC603E7TEC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| MPC603E7TED | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| mpc603efe100ln | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MPC603EFE100TN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Specifications |
| MPC603EFE133LN | 制造商:Motorola Inc 功能描述: |
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