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PowerPC 603e RISC Microprocessor Technical Summary
Part 1 PowerPC 603e Microprocessor Overview
This section describes the features of the 603e, provides a block diagram showing the major functional units,
and gives an overview of how the 603e operates.
The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set
computer (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture,
which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data
types of 32 and 64 bits.
The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.
The fourth is a dynamic power management mode that causes the functional units in the 603e to
automatically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The 603e is a superscalar processor that can issue and retire as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the 603e makes completion
appear sequential.
The 603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five
instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency
and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is
pipelined so a single-precision multiply-add instruction can be issued and completed every clock cycle.
The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches
for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603e also
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603e provides a
three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol
is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers
for memory accesses, and supports memory-mapped I/O operations.
The 603e is fabricated using an advanced CMOS process technology and is fully compatible with TTL
devices. The 603e is implemented in both a 2.5-volt version (PID 0007v PowerPC 603e microprocessor, or
PID7v-603e) and a 3.3-volt version (PID 0006 PowerPC 603e microprocessor, or PID6-603e).