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参数资料
| 型号： | MPC603E |
| 厂商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微处理器的PowerPC 603e |
| 文件页数： | 9/31页 |
| 文件大小： | 132K |
| 代理商： | MPC603E |
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PowerPC 603e RISC Microprocessor Technical Summary
9
1.5.2 Cache Units
The 603e provides independent 16-Kbyte, four-way set-associative instruction and data caches. The cache
block is 32 bytes long. The caches adhere to a write-back policy, but the PowerPC architecture allows
control of cacheability, write policy, and memory coherency at the page and block levels. The caches use a
least recently used (LRU) replacement policy.
As shown in Figure 1, the caches provide a 64-bit interface to the instruction fetch unit and load/store unit.
The surrounding logic selects, organizes, and forwards the requested information to the requesting unit.
Write operations to the cache can be performed on a byte basis, and a complete read-modify-write operation
to the cache can occur in each cycle.
The load/store and instruction fetch units provide the caches with the address of the data or instruction to
be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.
Since the 603e data cache tags are single ported, simultaneous load or store and snoop accesses cause
resource contention. Snoop accesses have the highest priority and are given first access to the tags, unless
the snoop access coincides with a tag write, in which case the snoop is retried and must re-arbitrate for
access to the cache. Loads or stores that are deferred due to snoop accesses are executed on the clock cycle
following the snoop.
1.6 Processor Bus Interface
Memory accesses can occur in single-beat (1–8 bytes) and four-beat burst (32 bytes) data transfers when the
bus is configured as 64 bits, and in single-beat (1–4 bytes), two-beat (8 bytes), and eight-beat (32 bytes) data
transfers when the bus is configured as 32 bits. The address and data buses operate independently to support
pipelining and split transactions during memory accesses. The 603e can pipeline its bus transactions to a
depth of one level.
Because the caches on the 603e are on-chip, write-back caches, the predominant type of transaction for most
applications is burst-read memory operations, followed by burst-write memory operations, and single-beat
(noncacheable or write-through) memory read and write operations. Additionally, there can be address-only
operations, variants of the burst and single-beat operations, (for example, global memory operations that are
snooped and atomic memory operations), and address retry activity (for example, when a snooped read
access hits a modified line in the cache).
Access to the system interface is granted through an external arbitration mechanism that allows devices to
compete for bus mastership. This arbitration mechanism is flexible, allowing the 603e to be integrated into
systems that implement various fairness and bus parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and
multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of the
bus without sacrificing coherency of the data. The 603e allows read operations to precede store operations
(except when a dependency exists, or in cases where a non-cacheable access is performed), and provides
support for a write operation to proceed a previously queued read data tenure (for example, allowing a snoop
push to be enveloped by the address and data tenures of a read operation). Because the processor can
dynamically optimize run-time ordering of load/store traffic, overall performance is improved.
1.7 System Support Functions
The 603e implements several support functions that include power management, time base/decrementer
registers for system timing tasks, an IEEE 1149.1(JTAG)/common on-chip processor (COP) test interface,
and a phase-locked loop (PLL) clock multiplier. These system support functions are described in the
following subsections.
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相关代理商/技术参数 |
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|---|---|
| MPC603E7TEC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| MPC603E7TED | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| mpc603efe100ln | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MPC603EFE100TN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Specifications |
| MPC603EFE133LN | 制造商:Motorola Inc 功能描述: |
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