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参数资料
| 型号： | MPC603E |
| 厂商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微处理器的PowerPC 603e |
| 文件页数： | 18/31页 |
| 文件大小： | 132K |
| 代理商： | MPC603E |
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PowerPC 603e RISC Microprocessor Technical Summary
2.4 Cache Implementation
The following subsections describe the PowerPC architecture’s treatment of cache in general, and the 603e-
specific implementation, respectively.
2.4.1 PowerPC Cache Characteristics
The PowerPC architecture does not define hardware aspects of cache implementations. For example, some
PowerPC processors, including the 603e, have separate instruction and data caches (Harvard architecture),
while others, such as the PowerPC 601
microprocessor, implement a unified cache.
PowerPC microprocessors control the following memory access modes on a page or block basis:
Write-back/write-through mode
Caching-inhibited mode
Memory coherency
Note that in the 603e, a cache block is defined as eight words. The VEA defines cache management
instructions that provide a means by which the application programmer can affect the cache contents.
2.4.2 PowerPC 603e Microprocessor Cache Implementation
The 603e has two 16-Kbyte, four-way set-associative (instruction and data) caches. The caches are
physically addressed, and the data cache can operate in either write-back or write-through mode as specified
by the PowerPC architecture.
The data cache is configured as 128 sets of 4 blocks each. Each block consists of 32 bytes, two state bits,
and an address tag. The two state bits implement the three-state MEI (modified/exclusive/invalid) protocol.
Each block contains eight 32-bit words. Note that the PowerPC architecture defines the term block as the
cacheable unit. For the 603e, the block size is equivalent to a cache line. A block diagram of the data cache
organization is shown in Figure 3.
The instruction cache also consists of 128 sets of 4 blocks, and each block consists of 32 bytes, an address
tag, and a valid bit. The instruction cache may not be written to except through a block fill operation. The
instruction cache is not snooped, and cache coherency must be maintained by software. A fast hardware
invalidation capability is provided to support cache maintenance. The organization of the instruction cache
is very similar to the data cache shown in Figure 3.
Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary
(that is, bits A27–A31 of the effective addresses are zero); thus, a cache block never crosses a page
boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The 603e’s cache blocks are loaded in four beats of 64 bits each when the 603e is configured with a 64-bit
data bus; when the 603e is configured with a 32-bit bus, cache block loads are performed with eight beats
of 32 bits each. The burst load is performed as “critical double-word first.” The data cache is blocked to
internal accesses until the load completes; the instruction cache allows sequential fetching during a cache
block load. The critical double word is simultaneously written to the cache and forwarded to the requesting
unit, thus minimizing stalls due to load delays.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC603E7TEC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| MPC603E7TED | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| mpc603efe100ln | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MPC603EFE100TN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Specifications |
| MPC603EFE133LN | 制造商:Motorola Inc 功能描述: |
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