PowerPC 603e RISC Microprocessor Technical Summary
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contents of the rename registers to the appropriate FPR when floating-point instructions are retired by the
completion unit.
The 603e supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero, and
infinity) in hardware, eliminating the latency incurred by software exception routines. (Note that exception
is also referred to as interrupt in the architecture specification.)
1.4.3 Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface between the GPRs,
FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment,
and provides sequencing for load/store string and multiple instructions.
Load and store instructions are issued and translated in program order; however, the actual memory accesses
can occur out of order. Synchronizing instructions are provided to enforce strict ordering.
Cacheable loads, when free of data dependencies, execute in a speculative manner with a maximum
throughput of one per cycle and a two-cycle total latency. Data returned from the cache is held in a rename
register until the completion logic commits the value to a GPR or FPR. Stores cannot be executed out of
order and are held in the store queue until the completion logic signals that the store operation is to be
completed to memory. The 603e executes store instructions with a maximum throughput of one per cycle
and a three-cycle total latency. The time required to perform the actual load or store operation varies
depending on the processor/bus clock ratio, and whether the operation involves the cache, system memory,
or an I/O device.
1.4.4 System Register Unit (SRU)
The SRU executes various system-level instructions, including condition register logical operations and
move to/from special-purpose register instructions, and also executes integer add/compare instructions. In
order to maintain system state, most instructions executed by the SRU are completion-serialized; that is, the
instruction is held for execution in the SRU until all prior instructions issued have completed. Results from
completion-serialized instructions executed by the SRU are not available or forwarded for subsequent
instructions until the instruction completes.
1.4.5 Completion Unit
The completion unit tracks instructions from dispatch through execution, and then retires, or “completes,”
them in program order. Completing an instruction commits the 603e to any architectural register changes
caused by that instruction. In-order completion ensures the correct architectural state when the 603e must
recover from a mispredicted branch or any exception.
Instruction state and other information required for completion is kept in a first-in-first-out (FIFO) queue of
five completion buffers. A single completion buffer entry is allocated for each instruction once it enters the
dispatch unit. A completion buffer entry is required for instruction dispatch; otherwise, instruction dispatch
stalls. A maximum of two instructions per cycle are completed in order from the queue.
1.5 Memory Subsystem Support
The 603e provides support for cache and memory management through dual instruction and data memory
management units. The 603e also provides dual 16-Kbyte instruction and data caches, and an efficient
processor bus interface for access into main memory and other bus subsystems. The memory subsystem
support functions are described in the following subsections.