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参数资料
| 型号： | MPC603E |
| 厂商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微处理器的PowerPC 603e |
| 文件页数： | 3/31页 |
| 文件大小： | 132K |
| 代理商： | MPC603E |
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PowerPC 603e RISC Microprocessor Technical Summary
3
1.1 PowerPC 603e Microprocessor Features
This section describes details of the 603e’s implementation of the PowerPC architecture. Major features of
the 603e are as follows:
High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR), and integer add/
compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
— Hardware support for misaligned little-endian accesses (PID7v-603e)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC603E7TEC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| MPC603E7TED | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 603e RISC Microprocessor |
| mpc603efe100ln | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MPC603EFE100TN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Specifications |
| MPC603EFE133LN | 制造商:Motorola Inc 功能描述: |
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