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参数资料
| 型号： | MPM22CGA800A |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, XMA |
| 封装： | MMC-2 |
| 文件页数： | 22/68页 |
| 文件大小： | 966K |
| 代理商： | MPM22CGA800A |
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Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep Technology
243356-006
Datasheet
23
is always device #0, AD11 will never be asserted during PCI configuration cycles as an IDSEL.
The 82443BX reserves AD12 for the AGPbus. Thus, AD13 is the first available address line usable
as an IDSEL. Intel recommends that AD18 be used by the PIIX4E/M.
4.3.4
AGP Interface
The 82443BX Host Bridge system controller is compliant with the AGP Interface Specification
Revision 2.0, which supports an asynchronous AGP interface coupling to the 82443BX core
frequency. The AGP interface can achieve real data throughput in excess of 500 MB per second
using an AGP 2X graphics device. Actual bandwidth may vary depending on specific hardware
and software implementations.
4.4
Intel SpeedStep Technology
Intel Speedstep technology allows the processor to switch between two core frequencies without
resetting the processor or changing the system bus frequency. The processor has two bus ratios
programmed instead of one. A lower frequency mode maximizes battery life, and a higher
frequency mode provides processor performance similar to desktop Pentium III processor systems.
The high performance mode should be used when the system is connected to an external power
source because this mode requires more power. More cooling may be required as well. For
example, it may be necessary to switch from passive to active cooling when using the high
performance mode. For more detailed technical information regarding Intel SpeedStep technology,
refer to the Geyserville Hardware Technical Specification Rev. 2.0 (OR-1728) and the Geyserville
Software Architecture Specification Rev 1.5 (SC-2364).
4.5
Power Management
4.5.1
Clock Control Architecture
The clock control architecture has been optimized for notebook designs. The clock control
architecture consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep. The Auto Halt state provides a low-power clock state
that can be controlled through the software execution of the HLT instruction. The Quick Start state
provides a very low-power, low-exit latency clock state that can be used for hardware controlled
"idle" states. The Deep Sleep state provides an extremely low-power state that can be used for
Power-On-Suspend states, which is an alternative to shutting off the processor’s power. The exit
latency of the Deep Sleep state is 30
S. The Stop Grant state and the Quick Start clock states are
mutually exclusive. For example, a strapping option on signal A15# chooses which state is entered
when the STPCLK# signal is asserted. Strapping the A15# signal to ground at Reset enables the
Quick Start state. Otherwise, asserting the STPCLK# signal puts the processor into the Stop Grant
state.
Table 15 provides information on the clock control states, and Figure 3 illustrates the clock control
architecture. Performing state transitions not shown in Figure 3 are neither recommended nor
supported.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPM-25S | 制造商:MPD 制造商全称:MicroPower Direct, LLC 功能描述:Universal Input, 25W Miniature, PC Mount AC/DC Power Supplies |
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| MPM-25S-12 | 制造商:MPD 制造商全称:MicroPower Direct, LLC 功能描述:Universal Input, 25W Miniature, PC Mount AC/DC Power Supplies |
| MPM-25S-15 | 制造商:MPD 制造商全称:MicroPower Direct, LLC 功能描述:Universal Input, 25W Miniature, PC Mount AC/DC Power Supplies |
| MPM-25S-24 | 制造商:MPD 制造商全称:MicroPower Direct, LLC 功能描述:Universal Input, 25W Miniature, PC Mount AC/DC Power Supplies |
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