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参数资料
| 型号： | MT28F200B3 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 闪存 |
| 文件页数： | 12/31页 |
| 文件大小： | 558K |
| 代理商： | MT28F200B3 |
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12
2Mb Smart 3 Boot Block Flash Memory
F48.p65 – Rev. 1/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb
SMART 3 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
Commands are issued to bring the device into differ-
ent operational modes. Each mode allows specific op-
erations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the properties
of each mode, and Table 3 lists all command sequences
required to perform the desired operation.
READ ARRAY
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFH) must be given to
return to the array read mode. Unlike the WRITE SETUP
command (40H), READ ARRAY does not need to be
given before each individual read access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90H) may be written to the CEL
to enter the identify device mode. While the device is
in this mode, any READ will produce the device ID
when A0 is HIGH and manufacturer compatibility ID
when A0 is LOW. The device will remain in this mode
until another command is given.
Table 3
Command Sequences
BUS
CYCLES
REQ’D
1
3
2
1
2
2
2
2
1ST
CYCLE
2ND
CYCLE
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
DATA OPERATION ADDRESS
FFH
90H
READ
70H
READ
50H
20H
WRITE
B0H
WRITE
40H
WRITE
10H
WRITE
DATA
NOTES
1
2, 3
4
X
X
X
X
X
X
X
X
IA
X
ID
SRD
BA
X
WA
WA
D0H
D0H
WD
WD
5, 6
6, 7
6, 7
NOTE:
1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable flash array READ cycles.
2. IA = Identify Address: 00H for manufacturer compatibility ID; 01H for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. On x16 (X00) devices BA = Block Address (A12-A16), on x8 (00X) devices BA = Block Address (A13-A16/A17).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
WRITE SEQUENCE
Two consecutive cycles are needed to write data to
the array. WRITE SETUP (40H or 10H) is given in the
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and V
PP
is brought
to V
PPH
. Writing to the boot block also requires that the
RP# pin be brought to V
HH
or that the WP# pin be
brought HIGH at the same time V
PP
is brought to V
PPH
.
The ISM will now begin to write the word or byte. V
PP
must be held at V
PPH
until the WRITE is completed
(SR7 = 1).
While the ISM executes the WRITE, the ISM status
bit (SR7) will be at “0,” and the device will not respond
to any commands. Any READ operation will produce
the status register contents on DQ0-DQ7. When the
ISM status bit (SR7) is set to a logic 1, the WRITE has
been completed, and the device will go into the status
register read mode until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the
part. Doing either during a WRITE will corrupt the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
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