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参数资料
| 型号： | MT28F200B3 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 闪存 |
| 文件页数： | 9/31页 |
| 文件大小： | 558K |
| 代理商： | MT28F200B3 |
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9
2Mb Smart 3 Boot Block Flash Memory
F48.p65 – Rev. 1/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb
SMART 3 BOOT BLOCK FLASH MEMORY
After power-up or RESET, the device will automati-
cally be in the array read mode. All commands and their
operations are covered in the Command Set and Com-
mand Execution sections.
STATUS REGISTER
Performing a READ of the status register requires the
same input sequencing as a READ of the array except
that the address inputs are “Don’t Care.” The status
register contents are always output on DQ0-DQ7, re-
gardless of the condition of BYTE# on the MT28F200B3.
DQ8-DQ15 are LOW when BYTE# is HIGH, and DQ8-
DQ14 are High-Z when BYTE# is LOW. Data from the
status register is latched on the falling edge of OE# or
CE#, whichever occurs last. If the contents of the status
register change during a READ of the status register,
either OE# or CE# may be toggled while the other is
held LOW to update the output.
Following a WRITE or ERASE, the device automati-
cally enters the status register read mode. In addition,
a READ during a WRITE or ERASE will produce the
status register contents on DQ0-DQ7. When the device
is in the erase suspend mode, a READ operation will
produce the status register contents until another com-
mand is issued. While the device is in certain other
modes, READ STATUS REGISTER may be given to re-
turn to the status register read mode. All commands
and their operations are covered in the Command Set
and Command Execution sections.
IDENTIFICATION REGISTER
A READ of the two 8-bit device identification regis-
ters requires the same input sequencing as a READ of
the array. WE# must be HIGH, and OE# and CE# must
be LOW. However, ID register data is output only on
DQ0-DQ7, regardless of the condition of BYTE# on the
MT28F200B3. A0 is used to decode between the two
bytes of the device ID register; all other address inputs
are “Don’t Care.” When A0 is LOW, the manufacturer
compatibility ID is output, and when A0 is HIGH, the
device ID is output. DQ8-DQ15 are High-Z when BYTE#
is LOW. When BYTE# is HIGH, DQ8-DQ15 are 00H
when the manufacturer compatibility ID is read and
22H when the device ID is read.
To get to the identification register read mode,
READ IDENTIFICATION may be issued while the device
is in certain other modes. In addition, the identifica-
tion register read mode can be reached by applying a
super-voltage (V
ID
) to the A9 pin. Using this method,
the ID register can be read while the device is in any
mode. Once A9 is returned to V
IL
or V
IH
, the device will
return to the previous mode.
held at V
HH
or the WP# pin held HIGH until the ERASE
or WRITE is completed. The V
PP
pin must be at V
PPH
(3.3V or 5V) when the boot block is written to or erased.
The MT28F002B3 and MT28F200B3 are available in
two configurations and top or bottom boot block. The
top boot block version supports processors of the x86
variety. The bottom boot block version is intended for
680X0 and RISC applications. Figure 1 illustrates the
memory address maps associated with these two ver-
sions.
PARAMETER BLOCKS
The two 8KB parameter blocks store less sensitive
and more frequently changing system parameters and
also may store configuration or diagnostic coding.
These blocks are enabled for erasure when the V
PP
pin
is at V
PPH
. No super-voltage unlock or WP# control is
required.
MAIN MEMORY BLOCKS
The two remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These
blocks are intended for code storage, ROM-resident
applications or operating systems that require in-
system update capability.
OUTPUT (READ) OPERATIONS
The MT28F002B3 and MT28F200B3 feature three
different types of READs. Depending on the current
mode of the device, a READ operation will produce data
from the memory array, status register or device iden-
tification register. In each of these three cases, the WE#,
CE# and OE# inputs are controlled in a similar manner.
Moving between modes to perform a specific READ is
covered in the Command Execution section.
MEMORY ARRAY
To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data will be output
on the DQ pins once these conditions have been met
and a valid address is given. Valid data will remain on
the DQ pins until the address changes, or until OE# or
CE# goes HIGH, whichever occurs first. The DQ pins
will continue to output new data after each address
transition as long as OE# and CE# remain LOW.
The MT28F200B3 features selectable bus widths.
When the memory array is accessed as a 128K x 16,
BYTE# is HIGH, and data will be output on DQ0-DQ15.
To access the memory array as a 256K x 8, BYTE# must
be LOW, DQ8-DQ14 are High-Z, and all data is output
on DQ0-DQ7. The DQ15/(A - 1) pin becomes the lowest
order address input so that 262,144 locations can be
read.
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相关代理商/技术参数 |
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|---|---|
| MT28F200B5 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH MEMORY |
| MT28F200B5SG-6 B | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-6 T | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-8 B TR | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 5V 2M-Bit 256K x 8/128K x 16 80ns 44-Pin SOP T/R |
| MT28F320A18 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH MEMORY |
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