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参数资料
| 型号： | MT46H128M32LFCM-5AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 14/106页 |
| 文件大小： | 3431K |
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Ball Descriptions
The ball descriptions table is a comprehensive list of all possible balls for all supported
packages. Not all balls listed are supported for a given package.
Table 3: Ball Descriptions
Symbol
Type
Description
CK, CK#
Input
Clock: CK is the system clock input. CK and CK# are differential clock inputs. All ad-
dress and control input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#. Input and output data is referenced to the crossing of
CK and CK# (both directions of the crossing).
CKE
CKE0, CKE1
Input
Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals,
input buffers, and output drivers. Taking CKE LOW enables PRECHARGE power-down
and SELF REFRESH operations (all banks idle), or ACTIVE power-down (row active in
any bank). CKE is synchronous for all functions except SELF REFRESH exit. All input buf-
fers (except CKE) are disabled during power-down and self refresh modes.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
CS#
CS0#, CS1#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for ex-
ternal bank selection on systems with multiple banks. CS# is considered part of the
command code.
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
UDM, LDM (x16)
DM[3:0] (x32)
Input
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM balls are input-only, the DM loading is
designed to match that of DQ and DQS balls.
BA0, BA1
Input
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0 and BA1 also determine which mode reg-
ister is loaded during a LOAD MODE REGISTER command.
A[13:0]
Input
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ or WRITE commands, to select one
location out of the memory array in the respective bank. During a PRECHARGE com-
mand, A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE REGISTER command. The maximum address range is de-
pendent upon configuration. Unused address balls become RFU.
TEST
Input
Test pin: Must be tied to VSS or VSSQ in normal operations.
DQ[15:0] (x16)
DQ[31:0] (x32)
Input/
output
Data input/output: Data bus for x16 and x32.
LDQS, UDQS (x16)
DQS[3:0] (x32)
Input/
output
Data strobe: Output with read data, input with write data. DQS is edge-aligned with
read data, center-aligned in write data. It is used to capture data.
TQ
Output
Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.
VDDQ
Supply
DQ power supply.
2Gb: x16, x32 Mobile LPDDR SDRAM
Ball Descriptions
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46H16M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
| MT46H16M16LF | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
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