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| 型号： | MT46H128M32LFCM-5AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 39/106页 |
| 文件大小： | 3431K |
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5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference voltage level for signals other than CK/
CK# is VDDQ/2.
6. A CK and CK# input slew rate
≥1 V/ns (2 V/ns if measured differentially) is assumed for
all parameters.
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (tCK + tAC) after the
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 × tCK + tAC) after the first clock at which the READ command was registered.
9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VDDQ/2 or to the crossing point for CK/CK#. The output tim-
ing reference voltage level is VDDQ/2.
10. Clock frequency change is only permitted during clock stop, power-down, or self refresh
mode.
11. In cases where the device is in self refresh mode for tCKE, tCKE starts at the rising edge
of the clock and ends when CKE transitions HIGH.
12. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round up to the
next highest integer.
13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8].
For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/
DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to tDS
and tDH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, func-
tionality is uncertain.
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and ad-
dresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to
VIL(AC) for falling input signals.
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ,
and tQH (tHP - tQHS). The data valid window derates directly proportional with the clock
duty cycle and a practical data valid window can be derived. The clock is provided a max-
imum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio.
18. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and
CK# inputs, collectively.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions.
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (tHZ) or begins driving (tLZ).
20. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
21. Fast command/address input slew rate
≥1 V/ns. Slow command/address input slew rate
≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an addi-
tional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps
added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain.
22. READs and WRITEs with auto precharge must not be issued until tRAS (MIN) can be satis-
fied prior to the internal PRECHARGE command being issued.
23. This is not a device limit. The device will operate with a negative value, but system per-
formance could be degraded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were pre-
viously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH
during this time, depending on tDQSS.
2Gb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46H16M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
| MT46H16M16LF | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
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