参数资料
型号: MT46H128M32LFCM-5AT:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA90
封装: 10 X 13 MM, GREEN, PLASTIC, VFBGA-90
文件页数: 69/106页
文件大小: 3431K
Partial-Array Self Refresh
For further power savings during self refresh, the partial-array self refresh (PASR) fea-
ture enables the controller to select the amount of memory to be refreshed during self
refresh. The refresh options include:
Full array: banks 0, 1, 2, and 3
One-half array: banks 0 and 1
One-quarter array: bank 0
One-eighth array: bank 0 with row address most significant bit (MSB) = 0
One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
READ and WRITE commands can still be issued to the full array during standard opera-
tion, but only the selected regions of the array will be refreshed during self refresh. Data
in regions that are not selected will be lost.
Output Drive Strength
Because the device is designed for use in smaller systems that are typically point-to-
point connections, an option to control the drive strength of the output buffers is
provided. Drive strength should be selected based on the expected loading of the mem-
ory bus. The output driver settings are
25Ω, 37Ω, and 55Ω internal impedance for full,
three-quarter, and one-half drive strengths, respectively.
2Gb: x16, x32 Mobile LPDDR SDRAM
Extended Mode Register
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
65
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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