参数资料
型号: MT46H128M32LFCM-5AT:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA90
封装: 10 X 13 MM, GREEN, PLASTIC, VFBGA-90
文件页数: 98/106页
文件大小: 3431K
Figure 52: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
tDQSS (NOM)
CK
CK#
Command1
WRITE2
NOP
Address
Bank a,
Col b
Bank
(a or all)
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
DQ7
DQS5, 6
DM6
tDQSS (MIN)
DQ7
DQS5, 6
DM6
tDQSS (MAX)
DQ7
DQS5, 6
DM6
tDQSS
Don’t Care
Transitioning Data
DIN
b
DIN
b
DIN
b
tWR4
PRE3
T4n
T3n
Notes: 1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. DINb = data-in for column b.
2Gb: x16, x32 Mobile LPDDR SDRAM
WRITE Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
91
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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