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参数资料
| 型号： | MT46H128M32LFCM-5AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 54/106页 |
| 文件大小： | 3431K |
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Truth Tables
Table 18: Truth Table – Current State Bank n – Command to Bank n
Notes 1–6 apply to all parameters in this table
Current State
CS#
RAS# CAS#
WE# Command/Action
Notes
Any
H
X
DESELECT (NOP/continue previous operation)
L
H
NO OPERATION (NOP/continue previous operation)
Idle
L
H
ACTIVE (select and activate row)
L
H
AUTO REFRESH
L
LOAD MODE REGISTER
Row active
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE (deactivate row in bank or banks)
Read (auto pre-
charge disabled)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE (truncate READ burst, start PRECHARGE)
L
H
L
BURST TERMINATE
Write (auto pre-
charge disabled)
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start new WRITE burst)
L
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
Notes: 1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh), after tXP has been met (if the previous state was power-
down), or after a full initialization (if the previous state was deep power-down).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown are supported for that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank,
must be issued on any clock edge occurring during these states. Supported commands to
any other bank are determined by that bank’s current state.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
2Gb: x16, x32 Mobile LPDDR SDRAM
Truth Tables
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
51
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
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| MT46H128M32LFCM-5IT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46V128M4FN-75E:C | 128M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT46V128M4P-75L:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V128M4P-75ZLIT:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46H16M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
| MT46H16M16LF | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
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