- 您现在的位置：买卖IC网 > PDF目录385639 > MT46V2M32V1 (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF资料下载
参数资料
| 型号： | MT46V2M32V1 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 2/65页 |
| 文件大小： | 2360K |
| 代理商： | MT46V2M32V1 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页
2
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
GENERAL DESCRIPTION
The 64Mb (x32) DDR SDRAM is a high-speed CMOS,
dynamic
random-access
67,108,864 bits. It is internally configured as a quad-
bank DRAM.
The 64Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2
n
-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 64Mb DDR SDRAM
effectively consists of a single 2
n
-bit wide, one-clock-
cycle data transfer at the internal DRAM core and two
corresponding
n
-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted ex-
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
The 64Mb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge
of CK. Commands (address and control signals) are
registered at every positive edge of CK. Input data is
registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
memory
containing
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE com-
mand are used to select the bank and the starting col-
umn location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, 8, or full page locations.
An auto precharge function may be enabled to provide
a self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V32M4-1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75L | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75Z | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75ZL | DOUBLE DATA RATE DDR SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M16 | 制造商:Micron Technology Inc 功能描述:32MX16 DDR SDRAM PLASTIC IND TEMP BGA 2.6V DDR - Trays |
| MT46V32M16-5B | 制造商:Micron Technology Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。