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参数资料
| 型号： | MT46V2M32V1 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 56/65页 |
| 文件大小： | 2360K |
| 代理商： | MT46V2M32V1 |
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56
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
TIMING PARAMETERS
-5
-6
-65
SYMBOL
t
CH
t
CL
t
CK (3)
t
CK (2)
t
IH
MIN
0.45
0.45
5
8
1
MAX
0.55
0.55
12
12
MIN
0.45
0.45
6
10
1
MAX
0.55
0.55
12
12
MIN
0.45
0.45
6.5
10
1
MAX
0.55
0.55
12
12
UNITS
t
CK
t
CK
ns
ns
ns
INITIALIZE AND LOAD MODE REGISTERS
-5
-6
-65
SYMBOL
t
IS
t
MRD
t
RFC
t
RP
t
VTD
MIN
1
2
66
20
0
MAX
MIN
1
2
66
18
0
MAX
MIN
1
2
66
19.5
0
MAX
UNITS
ns
t
CK
ns
ns
ns
CKE
LVCMOS
LOW LEVEL
DQ
BA0, BA1
200 cycles of CK
3
Load Extended
Mode Register
Load Mode
Register
2
t
MRD
t
MRD
t
RP
t
RFC
t
RFC
5
t
IS
Power-up:
V
DD
and
CK stable
T = 200μs
t
RP
High-Z
t
IH
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DQS
High-Z
A0-A7, A9, A10
RA
A8
RA
ALL BANKS
CK
CK#
t
CH
t
CL
t
CK
V
TT
1
tVTD
V
REF
V
DD
V
DD
Q
COMMAND
66
6
LMR
NOP
PRE
LMR
AR
AR
ACT
5
t
IS
t
IH
BA1 = L
tIS
tIH
t
IS
t
IH
BA1 = L
tIS
tIH
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CODE
CODE
tIS
tIH
CODE
CODE
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PRE
ALL BANKS
tIS
tIH
NOTE:
1. V
TT
is not applied directly to the device; however, tVTD must be greater than or equal to zero to avoid device latch-up.
2. JEDEC specifies resetting the DLL with A8 = H.
3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied after the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,
BA = Bank Address
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T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
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DON
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BA
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()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
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