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| 型号： | MT46V2M32V1 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 35/65页 |
| 文件大小： | 2360K |
| 代理商： | MT46V2M32V1 |
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35
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
Figure 25
PRECHARGE Command
PRECHARGE
The PRECHARGE command (Figure 25) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
t
RP) af-
ter the PRECHARGE command is issued. Input A8 de-
CS#
WE#
CAS#
RAS#
CKE
A8
BA0,BA1
HIGH
ALL BANKS
ONE BANK
BA
A0-A7, A9, A10
CK
CK#
BA = Bank Address (if A8 is LOW;
otherwise ( Don t Care )
t
IS
t
IS
No READ/WRITE
access in progress
Exit power-down mode
Enter power-down mode
CKE
CK
CK#
COMMAND
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
NOP
VALID
T0
T1
T2
Ta0
Ta1
Ta2
VALID
DON T CARE
termines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.
POWER-DOWN (CKE NOT ACTIVE)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times an access is in progress: from the
issuing of a READ or WRITE command until comple-
tion of the burst. For READs, a burst completion is de-
fined when the Read Postamble is satisfied; For
WRITEs, a burst completion is defined when the Write
Postamble is satisfied.
Power-down (Figure 26) is entered when CKE is reg-
istered LOW. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in any
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and out-
put buffers, excluding CK, CK# and CKE. For maximum
power savings, the DLL is frozen. Exiting power-down
requires the device to be at the same voltage and
frequancy as when it entered power-down. However,
power-down duration is limited by the refresh require-
ments of the device, so in most applications, the self-
refresh mode is preferred over the DLL-disabled power-
down mode.
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited
when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable com-
mand may be applied one clock cycle later.
Figure 26
Power-Down
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