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| 型号： | MT47H64M8B6-3ELAT:D |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, FBGA-60 |
| 文件页数： | 103/139页 |
| 文件大小： | 9398K |
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2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of Vref(DC) and the first crossing of Vih(AC) MIN. tDS nominal slew rate for a
falling signal is defined as the slew rate between the last crossing of Vref(DC) and the
first crossing of Vil(AC) MAX. If the actual signal is always earlier than the nominal slew
rate line between the shaded “Vref(DC) to AC region,” use the nominal slew rate for
the derating value (see Figure 30 (page 70)). If the actual signal is later than the nomi-
nal slew rate line anywhere between the shaded “Vref(DC) to AC region,” the slew rate
of a tangent line to the actual signal from the AC level to DC level is used for the derat-
ing value (see Figure 31 (page 70)).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of Vil(DC) MAX and the first crossing of Vref(DC). tDH nominal slew rate for a
falling signal is defined as the slew rate between the last crossing of Vih(DC) MIN and
the first crossing of Vref(DC). If the actual signal is always later than the nominal slew
rate line between the shaded “DC level to Vref(DC) region,” use the nominal slew rate
for the derating value (see Figure 32 (page 71)). If the actual signal is earlier than the
nominal slew rate line anywhere between shaded “DC to Vref(DC) region,” the slew
rate of a tangent line to the actual signal from the DC level to Vref(DC) level is used for
the derating value (see Figure 33 (page 71)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached Vih[AC]/Vil[AC] at the time of the rising clock transition), a valid
input signal is still required to complete the transition and reach Vih(AC)/Vil(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 32 (page 68) are the
DQS single-ended slew rate derating with DQS referenced at Vref and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to Vref is listed in Table 34 (page 69) and
Table 35 (page 69). Table 34 (page 69) provides the Vref-based fully derated values
fully derated values for the DQ (tDSa and tDHa) for DDR2-400.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
PDF: 09005aef82f1e6e2
Rev. N 1/09 EN
66
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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