参数资料
型号: MT47H64M8B6-3ELAT:D
元件分类: DRAM
英文描述: DDR DRAM, PBGA60
封装: 10 X 10 MM, ROHS COMPLIANT, FBGA-60
文件页数: 27/139页
文件大小: 9398K
Figure 71: Self Refresh
CK1
CK#
Command
NOP
REF
Address
CKE1
Valid
DQ
DM
DQS#, DQS
NOP4
tRP8
tCH
tCL
tCK1
tXSNR2, 5, 10
tISXR2
Enter self refresh
mode (synchronous)
Exit self refresh
mode (asynchronous)
T0
T1
Ta2
Ta1
Don’t Care
Ta0
Tc0
Tb0
tXSRD2, 7
Valid5
NOP4
tCKE (MIN)9
T2
ODT6
tAOFD/tAOFPD6
Td0
Valid7
Valid5
Indicates a break in
time scale
tIH
tCKE3
Notes: 1. Clock must be stable and meeting tCK specifications at least 1 × tCK after entering self
refresh mode and at least 1 × tCK prior to exiting self refresh mode.
2. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first ris-
ing clock edge where CKE HIGH satisfies tISXR.
3. CKE must stay HIGH until tXSRD is met; however, if self refresh is being re-entered, CKE
may go back LOW after tXSNR is satisfied.
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
which allows any nonREAD command.
5. tXSNR is required before any nonREAD command can be applied.
6. ODT must be disabled and Rtt off (tAOFD and tAOFPD have been satisfied) prior to enter-
ing self refresh at state T1.
7. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self
refresh.
10. Upon exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.
512Mb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH
PDF: 09005aef82f1e6e2
Rev. N 1/09 EN
122
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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