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| 型号： | MT47H64M8B6-3ELAT:D |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, FBGA-60 |
| 文件页数： | 39/139页 |
| 文件大小： | 9398K |
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ODT Timing
Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been ena-
bled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate either in synchronous mode or asynchronous mode, de-
pending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 83 (page 134).
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-
signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD
shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not
occur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing prior to entering any power-down mode is determined by the pa-
satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is
the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur
until state T3. When tANPD (MIN) is not satisfied, tAONPD timing parameters apply.
ODT turn-off timing after exiting any power-down mode is determined by the parame-
satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is
the example where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.
When tAXPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing after exiting either slow-exit power-down mode or precharge power-
down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing
not satisfied because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied,
tAONPD timing parameters apply.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
PDF: 09005aef82f1e6e2
Rev. N 1/09 EN
133
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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