- 您现在的位置：买卖IC网 > PDF目录385639 > MT49H8M32FM (Micron Technology, Inc.) REDUCED LATENCY DRAM RLDRAM PDF资料下载
参数资料
| 型号： | MT49H8M32FM |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | REDUCED LATENCY DRAM RLDRAM |
| 中文描述： | 低延迟DRAM延迟DRAM |
| 文件页数： | 6/43页 |
| 文件大小： | 652K |
| 代理商： | MT49H8M32FM |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页
6
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
BALL DESCRIPTIONS
T-FBGA (x32)
12J, 12K
2L
1J
1K
2K
11J, 11K, 2J
12G, 11G, 10G, 12G, 11G, 10G,
12H, 11H, 1G,
2G, 3G, 1H,
2H, 12M, 11M, 2H, 12M, 11M,
10M, 12L, 11L, 10M, 12L, 11L,
1M, 2M, 3M, 1L 1M, 2M, 3M,
T-FBGA (x16)
12J, 12K
2L
1J
1K
2K
11J, 11K, 2J
SYMBOL
CK, CK#
CS#
AS#
WE#
REF#
B[0:2]
A[0:18]
A[0:19]
TYPE
Input
Input
Input
Input
Input
Input
Input
DESCRIPTION
Differential input clock pair
Chip select
Address strobe
Write enable
Auto refresh
Bank select
Address input
12H, 11H, 1G,
2G, 3G, 1H,
12N, 1L
1F, 1N
11A
12V
1F, 1N
11A
12V
DM0, DM1
TMS
TDI
Input
Input
Data Mask
IEEE 1149.1 Test Inputs: JEDEC-standard 1.8V I/O levels.
These pins may be left Not Connected if the JTAG
function is not used in the circuit.
IEEE 1149.1 Clock Input: JEDEC-standard 1.8V I/O levels.
This pin must be tied to V
SS
if the JTAG function is not
used in the circuit.
Input Reference Voltage: Nominally V
DD
Q/2. Provides a
reference voltage for the input buffers.
Synchronous Data I/Os: Input data must meet setup and
hold times around the rising edges of CK and CK#.
Output data is synchronized to DQS and DQS#.
12A
12A
TCK
Input
3A, 3V
3A, 3V
V
REF
Input
11B, 10B, 11C, 11B, 10B, 11C,
10C, 11E, 10E,
11F, 10F, 2B,
3B, 2C, 3C, 2E, 10U, 11T, 10T,
3E, 2F, 3F, 2U,
3U, 2T, 3T, 2P,
3P, 2N, 3N,
11U, 10U, 11T,
10T, 11P, 10P,
11N, 10N
11D, 2D, 2R,
11R, 10D, 3D,
3R, 10R
DQ0–DQ31
Input/
Output
10C, 11E, 10E,
11F, 10F, 11U,
11P, 10P, 11N,
10N
11D, 11R,
10D, 10R
DQS0–3 (x32) Output
DQS#0–3 (x32)
DQS0–1 (x16)
DQS#0–1 (x16)
DVLD
TDO
V
EXT
Differential data read strobe
12F
11V
2A, 2V,
10A, 10V
3J, 3K, 4G,
4J, 4K, 4M,
9G, 9J, 9K,
9M, 10J, 10K
12F
11V
2A, 2V,
10A, 10V
3J, 3K, 4G,
4J, 4K, 4M,
9G, 9J, 9K,
9M, 10J, 10K
Output
Output
Supply
Data Valid
IEEE 1149.1 Test Output: JEDEC-standard 1.8V I/O level.
Power Supply: 2.5V nominal. See DC Electrical
Characteristics and Operating Condidtions for range.
Power Supply: 1.8V nominal. See DC Electrical
Characteristics and Operating Conditions for range.
V
DD
Supply
(continued on next page)
相关PDF资料 |
PDF描述 |
|---|---|
| MT4C1M16E5DJ-6 | EDO DRAM |
| MT4LC1M16E5DJ-6S | EDO DRAM |
| MT4LC1M16E5 | EDO DRAM |
| MT4C4256 | 256K x 4 DRAM Standard Or Low Power, Extended Refresh(标准或低功率，扩展刷新，256K x 4动态RAM) |
| MT4C4256L | 256K x 4 DRAM Standard Or Low Power, Extended Refresh(标准或低功率，扩展刷新，256K x 4动态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT49H8M32FM-33 ES | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 256MBIT 1.8V 144PIN UBGA - Trays |
| MT49H8M32FM-33 TR | 制造商:Micron Technology Inc 功能描述:8MX32 RLDRAM PLASTIC FBGA 1.8V COMMON I/O 8 BANKS 1.8V I/O - Tape and Reel |
| MT49H8M32FM-4 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 256MBIT 1.8V 144PIN UBGA - Trays |
| MT49H8M32FM-4 ES | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 256MBIT 1.8V 144PIN UBGA - Trays |
| MT49H8M32FM-5 ES | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 256MBIT 1.8V 144FBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。