参数资料
型号: MT49H8M32FM
厂商: Micron Technology, Inc.
英文描述: REDUCED LATENCY DRAM RLDRAM
中文描述: 低延迟DRAM延迟DRAM
文件页数: 9/43页
文件大小: 652K
代理商: MT49H8M32FM
9
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
PROGRAMMING DESCRIPTION
The following table shows, for three operating frequen-
cies, the different RLDRAM configurations that can be
programmed into the Mode Register. The Read Latency
(RL) values and the Write Latencies (WL) used by the
RLDRAM Programming Table
NOTE:
1. The speed sort -3.3 provides part functional up to 300 MHz in the configurations 4, 5,
and 6 only.
The functionality of the configurations 1, 2, and 3 is not guaranteed for speed sort -
3.3.
2. The speed sort -4 provides part functional up to 250 MHz in the configurations 3, 4, 5,
and 6 only.
The functionality of the configurations 1 and 2 is not guaranteed for speed sort -4.
3. The speed sort -5 provides part functional up to 200 MHz in all configurations.
RLDRAM for the two Burst Lengths (BL) are also indi-
cated. Finally, the minimum allowed
t
RC in clock cycles
and in ns are shown as well. The shaded areas correspond
to configurations that are not allowed.
FREQUENCY
-3.3 (300 MHz)
3
5
2
1
7
20.0
23.3
-4 (250 MHz)
2
3
5
5
2
2
1
1
6
7
24
28
-5 (200 MHz)
2
3
5
5
2
2
1
1
6
7
30
35
Unit
Config. Nb.
RL
WL (BL2)
WL (BL4)
t
RC (MIN)
t
RC (MIN)
1
5
2
1
5
2
5
2
1
6
4
6
3
2
8
5
7
4
3
9
6
8
5
4
10
33.3
TCK
TCK
TCK
TCK
ns
16.7
26.7
30.0
Config. Nb.
RL
WL (BL2)
WL (BL4)
t
RC (MIN)
t
RC (MIN)
1
5
2
1
5
20
4
6
3
2
8
32
5
7
4
3
9
36
6
8
5
4
10
40
TCK
TCK
TCK
TCK
ns
Config. Nb.
RL
WL (BL2)
WL (BL4)
t
RC (MIN)
t
RC (MIN)
1
5
2
1
5
25
4
6
3
2
8
40
5
7
4
3
9
45
6
8
5
4
10
50
TCK
TCK
TCK
TCK
ns
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