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参数资料
| 型号： | MT58L128V18PF-6 |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 128K X 18 STANDARD SRAM, 3.5 ns, PBGA165 |
| 封装： | FBGA-165 |
| 文件页数： | 4/25页 |
| 文件大小： | 647K |
| 代理商： | MT58L128V18PF-6 |
12
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_2.p65 – Rev. 8/00
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa pins and DQPa. BWb# enables WRITEs to DQb pins and DQPb. BWc# enables WRITEs to
DQc pins and DQPc. BWd# enables WRITEs to DQd pins and DQPd. DQPa and DQPb are only available on the x18 and x36
versions. DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
TRUTH TABLE
OPERATION
ADDRESS CE# CE2# CE2
ZZ
ADSP# ADSC# ADV# WRITE# OE# CLK
DQ
USED
DESELECT Cycle, Power-Down
None
H
X
L
X
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
X
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
H
X
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
X
L
H
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
H
X
L
H
L
X
L-H
High-Z
SNOOZE MODE, Power-Down
None
X
H
X
High-Z
READ Cycle, Begin Burst
External
L
H
L
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
H
L
X
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
L
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
L
H
L
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
L
H
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
L
X
H
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
L
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
L
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
L
X
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
L
X
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
L
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
L
X
H
L
X
L-H
D
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相关代理商/技术参数 |
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|---|---|
| MT58L128V18PT-7.5 | 制造商:Micron Technology Inc 功能描述: |
| MT58L128V32F1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128V32P1T-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L128V32P1T-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L128V36F1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
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