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参数资料
| 型号： | MT58L128V36P1B-4 |
| 元件分类： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 2.3 ns, PBGA119 |
| 封装： | 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119 |
| 文件页数： | 23/35页 |
| 文件大小： | 353K |
| 代理商： | MT58L128V36P1B-4 |
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4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_D.p65 – Rev. 10/01
2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION
The Micron SyncBurst SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 4Mb SyncBurst SRAMs integrate a
256K x 18, 128K x 32, or 128K x 36 SRAM core with
advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
(CE#), two additional chip enables for easy depth ex-
pansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#) and global
write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device,
BWa# controls DQas and DQPa; BWb# controls DQbs
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQas and DQPa; BWb# con-
trols DQbs and DQPb; BWc# controls DQcs and DQPc;
BWd# controls DQds and DQPd. GW# LOW causes all
bytes to be written. Parity bits are only available on the
x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state tKQHZ nanoseconds after the rising edge
of clock.
Micron’s 4Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
相关PDF资料 |
PDF描述 |
|---|---|
| MT58L32L36PT-7.5 | 32K X 36 CACHE SRAM, 4.2 ns, PQFP100 |
| MT58L512L18DS-7.5IT | 512K X 18 CACHE SRAM, 4 ns, PQFP100 |
| MT58L512L18DT-10IT | 512K X 18 CACHE SRAM, 5 ns, PQFP100 |
| MT58L512L18PB-6IT | 512K X 18 STANDARD SRAM, 3.5 ns, PBGA119 |
| MT58L512L18PS-7.5IT | 512K X 18 CACHE SRAM, 4 ns, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT58L128V36P1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L128V36P1F-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L128V36P1T-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L1MV18D | 制造商:MICRON 制造商全称:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM |
| MT58L1MY18D | 制造商:MICRON 制造商全称:Micron Technology 功能描述:16Mb SYNCBURST⑩ SRAM |
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