- 您现在的位置：买卖IC网 > PDF目录268181 > NAND01GR3B3CZA1 (STMICROELECTRONICS) 128M X 8 FLASH 1.8V PROM, 35 ns, PBGA63 PDF资料下载
参数资料
| 型号： | NAND01GR3B3CZA1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 35 ns, PBGA63 |
| 封装： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, VFBGA-63 |
| 文件页数： | 28/59页 |
| 文件大小： | 998K |
| 代理商： | NAND01GR3B3CZA1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页当前第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
34/59
Blocks Lock-Down
The Lock-Down feature provides an additional lev-
el of protection. A Locked-down block cannot be
unlocked by a software command. Locked-Down
blocks can only be unlocked by setting the Write
Protect signal to Low for a minimum of 100ns.
Only locked blocks can be locked-down. The com-
mand has no affect on unlocked blocks.
Refer to Figure 25., Command Latch AC Wave-
forms for details on how to issue the command.
Block Lock Status
In Block Lock mode (PRL High) the Block Lock
Status of each block can be checked by issuing a
Read Block Lock Status command (see Table
The command consists of:
■
one bus cycle to give the command code
■
three bus cysles to give the block address
After this, a read cycle will then output the Block
Lock Status on the I/O pins on the falling edge of
Chip Enable or Read Enable, whichever occurs
last. Chip Enable or Read Enable do not need to
be toggled to update the status.
The Read Block Lock Status command will not be
accepted while the device is busy (RB Low).
The device will remain in Read Block Lock Status
mode until another command is issued.
If the device is not in the Block Lock mode (PRL
Low) the Block Status can be read in the Status
Register using the Read Status Register com-
mand.
Figure 20. Read Block Lock Status Operation
Note: Three address cycles are required for 2,4 and 8 Gb devices. The 512Mb and 1Gb devices only require two address cycles.
Table 16. Block Lock Status
Note: X = Don’t Care.
Status
I/O7-I/O3
I/O2
I/O1
I/O0
Locked
X
0
1
0
Unlocked
X
1
0
Locked-Down
X
0
1
Unlocked in Locked-
Down Area
X1
0
1
I/O
R
Block Address, 3 cycles
ai08669
7Ah
Read Block Lock
Status Command
Add1
Add2
Add3
Dout
Block Lock Status
tWHRL
W
相关PDF资料 |
PDF描述 |
|---|---|
| NAND02GR4B2BZB1 | 128M X 16 FLASH 1.8V PROM, 35 ns, PBGA63 |
| NCH030A3-FREQ-OUT27 | CRYSTAL OSCILLATOR, CLOCK, 1 MHz - 4 MHz, HCMOS OUTPUT |
| NTHA3JAA3-FREQ-OUT27 | CRYSTAL OSCILLATOR, CLOCK, 1 MHz - 4 MHz, HCMOS OUTPUT |
| NTHA3KC3-FREQ-OUT27 | CRYSTAL OSCILLATOR, CLOCK, 1 MHz - 4 MHz, HCMOS OUTPUT |
| NCHA80C3-FREQ1-OUT27 | CRYSTAL OSCILLATOR, CLOCK, 24 MHz - 80 MHz, HCMOS OUTPUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GR3M0AZB5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZB5F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZC5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZC5F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0BZB5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
发布紧急采购，3分钟左右您将得到回复。