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参数资料
| 型号： | NAND01GR3B3CZA1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 35 ns, PBGA63 |
| 封装： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, VFBGA-63 |
| 文件页数： | 5/59页 |
| 文件大小： | 998K |
| 代理商： | NAND01GR3B3CZA1 |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures
where 32 cells are connected in series.
The memory array is organized in blocks where
each block contains 64 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a 2048 Byte
main area and a spare area of 64 Bytes. In the x16
devices the pages are split into a 1,024 Word main
area and a 32 Word spare area. Refer to Figure
Bad Blocks
The NAND Flash 2112 Byte/ 1056 Word Page de-
vices may contain Bad Blocks, that is blocks that
contain one or more invalid bits whose reliability is
not guaranteed. Additional Bad Blocks may devel-
op during the lifetime of the device.
The Bad Block Information is written prior to ship-
ping (refer to Bad Block Management section for
more details).
Table 4. shows the minimum number of valid
blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipped and the Bad Blocks that could de-
velop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to SOFTWARE ALGO-
RITHMS section).
Table 4. Valid Blocks
Figure 8. Memory Array Organization
Density of Device
Min
Max
8 Gbits
8032
8192
4 Gbits
4016
4096
2 Gbits
2008
2048
1Gbit
1004
1024
512 Mbits
502
512
AI09854
Block = 64 Pages
Page = 2112 Bytes (2,048 + 64)
2,048 Bytes
2048 Bytes
Spare
Area
64
Bytes
Block
8 bits
64
Bytes
8 bits
Page
Page Buffer, 2112 Bytes
Block = 64 Pages
Page = 1056 Words (1024 + 32)
1,024 Words
1024 Words
Spare
Area
Main Area
32
Words
16 bits
32
Words
16 bits
Page Buffer, 1056 Words
Block
Page
x8 DEVICES
x16 DEVICES
Main Area
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GR3M0AZB5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZB5F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZC5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZC5F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0BZB5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
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