参数资料
| 型号： | NCP5318FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5318FTR2GOSCT |
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NCP5318
The NCP5318 provides a differential input (CSxN and
CSxP) that accepts inductor current information for each
phase as shown in Figure 17. The triangular inductor current
When the technique known as “lossless inductor current
sensing” is used as in Figure 19, the magnitude of Ext_Ramp
is:
is measured across R S and amplified before being summed
with the channel startup offset, the internal ramp and the
Ext_Ramp + D
(VIN * VOUT) (RCSx
CCSx @ fSW)
) 3.0 V
D V + RS
GCSA
output voltage. The internal ramp provides greater design
flexibility by allowing smaller external (current) ramps,
lower minimum pulse widths, higher frequency operation
and PWM duty cycles above 50% without external slope
compensation.
When the controller is enabled, GATEx output (GATE
output of any phase) transitions to a high voltage at the start
of the oscillator cycle for that phase, commanding a power
stage to switch on. Inductor current in that power stage then
ramps up until the combination of startup offset voltage, its
current sense signal, its internal ramp and the output voltage
ripple exceed the compensated feedback signal at the other
PWM comparator input. This brings GATEx low, which
commands that power stage off. While GATEx is high, the
Enhanced V 2 control circuit will respond to line and load
variations, but once GATEx is low, that phase cannot
respond until the next start of its oscillator cycle. Therefore,
the NCP5318 will take, at most, the off ? time of the oscillator
to respond to disturbances. With multiple phases, the time to
respond to disturbances is significantly reduced due to the
increased likelihood of a GATEx being high, and closer
average proximity of oscillator starts, however the
magnitude of that response (for equivalent total inductance)
is equivalently reduced.
Turn on of a phase with higher inductor current will
terminate the PWM cycle earlier, providing negative
feedback. Current sharing is accomplished by referencing
the PWM comparators of all phases to the same Error
where D is duty cycle expressed as a fraction.
For example, if V OUT at zero load is set to 1.480 volts and
the input voltage V IN is 12.0 V, the duty cycle (D) will be
1.480/12.0 or 12.3%. Int_Ramp will be 100 mV/50% x
12.3% = 25 mV. Realistic values for R CSx , C CSx and f SW are
2.5 k W , 0.1 m F and 350 kHz. Using these and the previously
mentioned formula, Ext_Ramp will be 14.8 mV.
VCOMP + 1.480 V ) 0.60 V ) 25 mV
14.8 mV
V 2
+ 2.127 Vdc.
Error Amplifier Output (COMP) Voltage Bias Point
Change with Load
In a closed loop configuration, the COMP pin may move
in order to maintain the output voltage constant when load
current changes. The required change at the COMP pin
depends partially on the scaling of the current feedback
signal as follows:
D IOUT
N
where R S is the current sense resistance in each phase and
N is the number of phases.
Also, when load current changes, nonideal conversion
efficiency causes the change in input power to exceed the
change in output power, and the duty cycle becomes:
Amplifier signal (COMP pin).
Error Amplifier Output (COMP) Voltage No Load Bias
Point
and
D +
D
Efficiency
*
As shown in Figure 17, the voltage present at each PWM
comparator ’s non ? inverting input is the sum of the channel
startup offset, output voltage, and the inductor current and
internal ramps corresponding to that phase. When the
average output current is zero, the Error Amplifier output at
D D + D * D +
+
D (D Efficiency)
Efficiency Efficiency
D (1 * Efficiency)
Efficiency
) Int_Ramp ) GCSA
the COMP pin will be:
VCOMP + VOUT ) Channel_Startup_Offset
Ext_Ramp
2
Peak to peak ripple current therefore also changes by
nearly (1 ? Efficiency) / Efficiency, thereby changing the
amplitude of the external ramp by this amount. The
complete change required at the COMP pin will therefore
be:
D V + RS GCSA D IOUT )
Int_Ramp is the fraction of the internal ramp (“Artificial
Ramp Amplitude” = 100 mV at a 50% duty cycle)
corresponding to the steady state duty cycle, Ext_Ramp is the
peak ? to ? peak external steady ? state current ramp appearing
(Int_Ramp ) GCSA Ext_Ramp)
2
N
(1 * Efficiency )
Efficiency
across CSxP to CSxN, G CSA is the current sense amplifier
gain (“Current Sense Amp to PWM Gain” = 3.0 V/V).
http://onsemi.com
16
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