参数资料
| 型号： | NCP5318FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 24/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5318FTR2GOSCT |
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NCP5318
MAX dI/dt occurs in
first few PWM cycles.
V OUT
I Li
Vi(t = 0) = 12 V
Q1
SWNODE
I Lo
Vo(t = 0) = 1.480 V
Li
Lo
470 nH
NB IN × CB IN
+ Vi
? 12 V
+ V Ci
Q2
+
NB OUT × CB OUT
60 u(t)
ESR IN /NB IN
ESR OUT /NB OUT
Figure 24. Calculating the Input Inductance
D VCIN + ESRIN
Current changes slowly in the input inductor so the input
capacitors must initially deliver most of the input current.
The amount of voltage drop across the input capacitors
( D V CIN ) is determined by the number of bulk input
capacitors (NB IN ), their per capacitor ESR (ESR IN ) and the
current in the output inductor according to:
dlLo D (eq. 18)
NBIN dt fSW
Before the load is applied, the voltage across the input
inductor (V LIN ) is very small and the input capacitors charge
to the input voltage V IN . After the load is applied, the voltage
drop across the input capacitors, D V CIN , appears across the
input inductor as well. From this, the minimum value of the
input inductor can be calculated from:
6. MOSFET and Heatsink Selection
Power dissipation, package size and thermal requirements
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches with nearly zero
voltage. However, the body diode in the synchronous
MOSFET will incur diode losses during the non ? overlap
+ V dI LIN
+ D V dI CIN
LiMIN
IN
IN
( dt MAX )
( dt MAX )
(eq. 19)
time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL + (IRMS,CNTL2 RDS(on)) (eq. 20)
VIN
fSW)
) (ILo,MAX
) ( oss
VIN
fSW) ) (VIN @ QRR @ fSW)
dI IN /dt MAX is the maximum allowable input current
slew rate.
The input inductance value calculated from Equation 19
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality, input voltage
“sag,” lower capacitor ESRs and stray inductance will
further reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating. Also, for
an inexpensive iron powder core, such as the ? 26 or ? 52
from Micrometals, the inductance “swing” with DC bias
must be taken into account since inductance will decrease as
Qswitch
Ig
Q
2
The first term represents the conduction or I 2 R losses
when the MOSFET is ON while the second term represents
switching OFF losses. The third term is the loss associated
with charging the control and synchronous MOSFET output
capacitances when the control MOSFET turns ON. The
output losses are caused by the output capacitances of both
the control and synchronous MOSFET but are dissipated
only in the control FET. The fourth term is the loss due to the
reverse recovered charge of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
the DC input current increases. At the maximum input
current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
http://onsemi.com
24
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