参数资料
| 型号： | NCP5318FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 23/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5318FTR2GOSCT |
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NCP5318
The following equations will determine the maximum and
minimum currents delivered by the input capacitors:
In general, capacitor manufacturers require derating to the
specified ripple ? current based on the ambient temperature.
IC,MAX + Lo,MAX * IIN,AVG
IC,MIN + Lo,MIN * IIN,AVG
I
I
h
h
(eq. 8)
(eq. 9)
More capacitors will be required because of the current
derating.
5. Input Inductor Selection
The use of an inductor between the input capacitors and
ILo,MAX + O,MAX ) D ILo
I
f
2
ILo,MIN + O,MAX * D ILo
I
f
2
D ILo + (VIN * VOUT)
D
(Lo @ fSW)
) ) IIN,AVG2
D IC,IN2
) (1 * 4D)]1 2
VOUT,FULL ? LOAD +
VOUT,NO ? LOAD * (IO,MAX)
NCIN +
ICIN,RMS
IRMS,RATED
D VLo + VIN * VOUT,FULL ? LOAD
+ IN
) (IO,MAX)
I Lo,MAX is the maximum output inductor current:
(eq. 10)
where f is the number of phases in operation.
I Lo,MIN is the minimum output inductor current:
(eq. 11)
D I Lo is the peak ? to ? peak ripple current in the output
inductor of value Lo:
(eq. 12)
For the four ? phase converter, the input capacitor(s) RMS
current is then:
ICIN,RMS + [4D (IC,MIN2 ) IC,MIN D IC,IN (eq. 13)
3
Select the number of input capacitors (NC IN ) to provide
the RMS input current (I CIN,RMS ) based on the RMS ripple
current rating per capacitor (I RMS,RATED ):
(eq. 14)
For a four ? phase converter with perfect efficiency ( h = 1),
the worst case input ripple ? current will occur when the
converter is operating at a 12.5% duty cycle. At this
operating point, the parallel combination of input capacitors
must support an RMS ripple current equal to 12.5% of the
converter ’s DC output current. At other duty cycles, the
ripple ? current will be less. For example, at a duty cycle of
the power source isolates the voltage source and the system
from noise generated by the switching converter, while also
reducing the input current slew rate during load transients.
The worst case input current slew rate will occur during the
first few PWM cycles immediately after a step ? load change
is applied as shown in Figure 24. When the load is applied,
the output voltage is pulled down very quickly. Current
through the output inductors will not change
instantaneously, so the initial transient load current is
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I O,MAX ), the per capacitor ESR of the output
capacitors (ESR OUT ) and the number of bulk electrolytic
output capacitors (NB OUT ) as shown in Figure 24. The
output voltage at full transient load will be:
(eq. 15)
ESROUT
NBOUT
When the control MOSFET (Q1 in Figure 24) turns ON,
the input voltage will be applied to the input terminal of the
output inductor (the SWNODE). At that instant, the voltage
across the output inductor can be calculated as:
(eq. 16)
V * VOUT,NO ? LOAD
ESROUT
NBOUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
dILo + D VLo
either 6% or 19%, the four ? phase input ripple ? current will
be approximately 10% of the converter’s DC output current.
http://onsemi.com
23
dt Lo
(eq. 17)
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