参数资料
| 型号： | NCP5318FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5318FTR2GOSCT |
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NCP5318
VID
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients. In
addition, adaptive voltage positioning can reduce
peak ? peak output voltage deviations due to load transients
and allow use of a smaller output filter. Adaptive voltage
positioning sets output voltage higher than nominal at light
loads, and output voltage is allowed limited sag when the
load current is applied. Upon removal of the load, output
voltage returns no higher than the original level, allowing
one output transient peak to be canceled over a load
application and release cycle.
For low current applications, a simple dropping resistor in
series with the output can provide fast, accurate adaptive
positioning. However, at high currents, the loss in a dropping
resistor becomes excessive. For example, a 50 A converter
with a 1.0 m W resistor would provide a 50 mV change in
output voltage between no load and full load and would
dissipate 2.5 W. Lossless Adaptive Voltage Positioning
(AVP) is an alternative to using a droop resistor. Figure 20
shows how AVP works. The waveform labeled “normal”
shows a converter without AVP.
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 20. Adaptive Voltage Positioning
microseconds of a load transient is controlled primarily by
power stage output impedance, and by the ESR and ESL of
the output filter. The transition between fast and slow
positioning is controlled by the total ramp size and the error
amp compensation. If the ramp size is too large or the error
amp too slow, there will be a long transition to the final
voltage after a transient. This will be most apparent with low
capacitance output filters.
Overvoltage Protection
Overvoltage Protection (OVP) in the Enhanced V 2
control topology is provided by operation of the
synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This acts quickly to discharge the output
voltage and prevent damage to the load. The regulator will
remain in this state until the fault latch is reset by cycling
power at the V CC pin. If the voltage at the V FFB pin exceeds
200 mV above the VID voltage, the converter will latch off.
The OVP circuit begins monitoring the output voltage as
soon as the V CC voltage exceeds the UVLO threshold of the
part. The OVP circuit is then always active, regardless of
operating status.
Power Good
Power Good (PWRGD) is asserted when the voltage at the
PWRLS is greater then one half of the no load set point
voltage, and the voltage on the Vffb pin is less then the no
load set point voltage + 100 mV. The internal Power Good
comparator and logic circuitry is shown in Figure 21.
PWRLS
+
? Delay
2 2ms PWRGD
On the left, the output voltage sags when the output current
is stepped up and later overshoots when current is stepped
back down. With fast (ideal) AVP, the peak ? to ? peak
VID ) 100 mV
+
?
0 m s
excursions are cut in half. In the slow AVP waveform, the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded. The
controller can be configured to adjust the output voltage
based on the output current of the converter as shown in the
application diagram in Figure 1. The no ? load positioning is
set internally to VID ? 19 mV, reducing the potential error
due to resistor and bias current mismatches. In order to
realize the AVP function, a resistor divider network is
connected between V FB , V DRP and V OUT . During no ? load
conditions, the V DRP pin is at the same voltage as the V FB
pin. As the output current increases, the V DRP pin voltage
increases proportionally. This drives the V FB voltage higher,
causing V OUT to “droop” according to a loadline set by the
resistor divider network. The response during the first few
Vffb
Figure 21. Adjusting the PWRGD Threshold
V OUT
R1
PWRLS
R2
Figure 22. Adjusting the PWRGD Threshold
http://onsemi.com
19
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