参数资料
| 型号： | NCP5318FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5318FTR2GOSCT |
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NCP5318
100 A )
D VCOMP + 1.0 m W
For the converter described above with 4 phases and 85%
efficiency at 100 A full load, the Error Amplifier output
changes by:
3.0 V
V 4
(25 mV ) 3.0 V V 14.8 mV) (1 * 0.85)
2 0.85
+ 83 mV
Additionally, if the “Droop” feature is used, the output
voltage change resulting from the synthesized, closed loop
output impedance (referred to as the output loadline) is as
follows:
D V + * RLL D IOUT
where R LL is the value, in ohms, of the output loadline.
Summation of this change at the PWM comparator input
forces the Error Amplifier output voltage to respond with an
identical change which always opposes that forced by the
SWNODE
V FFB (V OUT )
Internal Ramp
CSA Out
COMP
CSA Output +
Internal Ramp +
Offset + CSxN
T1
sensed current previously described, which reduces the
amount of Error Amplifier output movement required.
Figure 18 shows the open loop response of the PWM
comparator and resulting phase current upon an output
voltage dip. Before T1, the converter is in steady ? state
operation. The inductor current provides a portion of the
PWM ramp through the current sense amplifier. The PWM
cycle ends when the sum of the current ramp, the “partial”
internal ramp, the offset and the output voltage exceeds the
level of the COMP pin. At T1, the load current increases and
the output voltage sags. The next PWM cycle begins and the
cycle continues longer than before until T2, when the current
signal has increased enough to make up for the lower voltage
at the VFB pin. After T2, the output voltage remains lower,
and the average current signal level (CSA output) is raised
so that the sum of the current and voltage signal is the same
as with the original load. In a closed loop system, the COMP
pin would move higher to restore the output voltage to the
original level.
T2
Figure 18. Open Loop Operation
http://onsemi.com
17
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