参数资料
| 型号： | NCP5318FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 08/Apr/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5318FTR2GOSCT |
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NCP5318
VLOWER + OUTNoLoad
An internal timer in the NCP5318 prevents the PWRGD
signal from being asserted for 2 ms (typically) from the time
that VOUT goes into range. If VOUT goes out of range,
PWRGD will be deasserted immediately (typically less than
2 m s).
The lower voltage threshold of the Power Good
comparator is externally programmable by adjusting
resistors R1 and R2 shown in Figure 22. The following
equations can be used to calculate the upper and lower
threshold voltages:
V R1 ) R2
2 R2
VUPPER + VOUTNoLoad ) 100 mV
Undervoltage Lockout
The NCP5318 includes an undervoltage lockout circuit.
This circuit keeps the IC’s output drivers low until V CC
applied to the IC reaches 9.0 V. The GATE outputs are
disabled when V CC drops below 8.0 V.
Soft ? Start
At initial power ? up, both SS and COMP voltages are zero.
The total SS capacitance will begin to charge with a current
of 70 m A. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper startup behavior. All GATE outputs are held
low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally.
Current Limit
The individual phase currents are summed to compare a
total current signal to a user adjustable voltage on the I LIM
pin. If the I LIM voltage is exceeded, the fault latch trips and
the converter is latched off. V CC must be recycled to reset the
latch.
Gate Outputs
The NCP5318 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5.0 ns.
An additional signal, DRVON, works in conjunction with
the Gate Outputs. The DRVON signal is intended to be used
as an enable signal for external gate drivers, such as the
NCP3418B. If the DRVON signal is low, the gate driver will
be disabled and both MOSFETs in the synchronous rectified
phase channel will be held in the off position. If the DRVON
signal is high, the gate driver will be enabled. The high side
MOSFET will be enabled if the Gate Output is high and
DRVON is high. The low side MOSFET will be enabled if
the Gate Output is low and DRVON is high. The DRVON
signal at power up will initially go high as V CC rises above
the power on reset (POR) of the IC, roughly 5 V. It will stay
high until the V CC voltage exceeds the UVLO threshold of
the part. DRVON will then go to a low state and stay low
until the part is enabled or an OVP is detected.
Digital to Analog Converter (DAC)
The output voltage of the NCP5318 is set by means of a
6 ? bit, 0.5% DAC. The VID pins must be pulled high
externally. A 1.0 k W pullup to a maximum of 3.3 V is
recommended to meet Intel specifications. To ensure valid
logic signals, the designer should ensure at least 800 mV will
be present at the IC for a logic high. The output of the DAC
is described in the Electrical Characteristics section of the
data sheet. These outputs are consistent with VR 10.x and
processor specifications. The DAC output is equal to the
VID code specification minus 19 mV. The latest VR and
processor specifications require a power supply to turn its
output off in the event of a 11111X VID code. When the
DAC sees such a code, the GATE pins stop switching and go
low. This condition is described in Table 1.
Fault Protection Logic
The NCP5318 includes fault protection circuitry to
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
Table 1. DESCRIPTION OF FAULT LOGIC
Results
Driver
SS Character-
Faults
Overvoltage Lockout
Enable Low
Module Overcurrent Limit
DAC Code = 11111x
V REF Undervoltage Lockout
PWRLS Out of Range
Stop Switching
Yes
Yes
Yes
Yes
Yes
No
PWRGD Level
Depends on output voltage level
Depends on output voltage level
Depends on output voltage level
Depends on output voltage level
De ? asserted
Enable
High
Low
Low
Low
Low
High
istics
? 0.3 mA
? 0.3 mA
? 0.3 mA
? 0.3 mA
? 0.3 mA
Not Affected
Reset Method
Power On
Not Affected
Power On
Change VID Code
Power On
Not Affected
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