参数资料
| 型号： | NCP5331FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH W/DRVRS 32-LQFP |
| 产品变化通告： | Product Obsolescence 05/Oct/2010 |
| 标准包装： | 1 |
| 应用： | 控制器，AMD Athlon? |
| 输入电压： | 9 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5331FTR2GOSCT |
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NCP5331
The waveforms in Figure 17 show a simulation of the
current sense signal and the actual inductor current during
a positive step in load current with values of L = 500 nH,
R L = 1.6 m W , RSx = 20 k and CSx = 0.01 m F. For ideal current
signal compensation the value of RSx should be 31 k W . Due
to the faster than ideal RC time constant there is an overshoot
of 50% and the overshoot decays with a 200 m s time
constant. With this compensation the I LIM pin threshold
must be set more than 50% above the full load current to
avoid triggering hiccup mode during a large output load
step.
Current Limit, Hiccup Mode and Overcurrent Timer
The individual phase currents are summed and low?pass
filtered to create an average current signal. The average
current is then compared to a user adjustable voltage at the
I LIM pin. If the I LIM voltage is exceeded, the fault latch is set,
Figure 17. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50 m s/div)
Figure 18. Hiccup Mode Operation
switching stops, and the COMP pin is discharged until it
decreases to 0.27 V. At this point, the fault latch is reset, the
COMP voltage will begin to rise and a new startup cycle
begins. During startup, the output voltage and load current
will increase until either regulation is achieved or the I LIM
voltage is again exceeded. The converter will continue to
operate in “hiccup mode” until the fault condition is
corrected or the overcurrent timer expires.
When an overcurrent fault occurs the converter will enter
a low duty cycle hiccup mode. During hiccup mode the
converter will not switch from the time a fault is detected
until the soft start capacitor (C C2 ) has discharged below the
COMP Discharge Threshold and then charged back up
above the Channel Start Up Offset. Figure 18 shows the
NCP5331 operating in hiccup mode with the converter
output shorted to GND. Hiccup mode will continue until the
overcurrent timer terminates operation.
The overcurrent timer sets a limit to how long the
converter will operate in hiccup mode. Placing a capacitor
from the C OVC pin to GND sets the length of time ? a larger
capacitor sets a longer time. The first hiccup pulse starts the
timer by turning on a current source that charges the
capacitor at the C OVC pin. If the voltage at the C OVC pin rises
to 3 V before the output voltage exceeds the PGD threshold,
then the overcurrent latch is set, COMP is discharged, and
PGD is latched Low. Once set, the overcurrent latch will
hold the converter in this state until the input voltage, either
V CCL or V CCH , is cycled. Conversely, if the timer starts and
either the output short circuit is removed or the load is
decreased before the overcurrent timer expires, PGD will
transition High after its programmed delay time and the
timer will be reset. The nominal overcurrent time can be
calculated using the following equation.
tOVC + COVC @ (OVCTHRESH * OVCMIN) IOVC
+ COVC @ (3.0 V * 0.25 V) 5.0 m A
+ COVC @ 5.5
105
Figure 19. Overcurrent Timer Operation
Figure 19 shows the overcurrent timer terminating hiccup
mode when C OVC charges up to 3.0 V.
http://onsemi.com
17
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