参数资料
| 型号： | NCP5331FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 26/36页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH W/DRVRS 32-LQFP |
| 产品变化通告： | Product Obsolescence 05/Oct/2010 |
| 标准包装： | 1 |
| 应用： | 控制器，AMD Athlon? |
| 输入电压： | 9 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5331FTR2GOSCT |
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NCP5331
MAX dI/dt occurs in
first few PWM cycles.
V OUT
I Li
Vi(t = 0) = 12 V
Q1
SWNODE
I Lo
Vo(t = 0) = 1.225 V
Li
TBD
Lo
729 nH
Ci
5 × 16MBZ1500M10X20
+ Vi
? 12 V
ESR Ci
13 m/5 = 2.6 m
+ V Ci
Q2
+ Co
6 × 16MBZ1000M10X16
26 u(t)
ESR Co
19 m/6 = 3.2 m
Figure 31. Calculating the Input Inductance
4. Input Inductor Selection
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors ( D V Ci ) is determined by the number of input
capacitors (N IN ), their per capacitor ESR (ESR IN ), and the
current in the output inductor according to
inrush currents will reduce the expected life of the input
capacitors. The inductor ’s limiting effect on the input
current slew rate becomes increasingly beneficial during
D VCi + ESRIN NIN @ dILo dt @ tON
+ ESRIN NIN @ dILo dt @ D fSW
(17)
LiMIN + VLi
dIIN dtMAX
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step?load
change is applied as shown in Figure 31. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
Before the load is applied, the voltage across the input
inductor (V Li ) is very small ? the input capacitors charge to
the input voltage, V IN . After the load is applied the voltage
drop across the input capacitors, D V Ci , appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from
(18)
step downward depending on the magnitude of the output
+ D VCi
dIIN dtMAX
VCORE,FULL?LOAD +
D VLo + VIN * VCORE,FULL?LOAD
current (I O,MAX ), the per capacitor ESR of the output
capacitors (ESR OUT ), and the number of the output
capacitors (N OUT ) as shown in Figure 31. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be
(14)
VCORE,NO?LOAD * (IO,MAX 2) @ ESROUT NOUT
When the control MOSFET (Q1 in Figure 31) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as
(15)
+ VIN * VCORE,NO?LOAD
) (IO,MAX 2) @ ESROUT NOUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from
where dI IN /dt MAX is the maximum allowable input current
slew rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the ?26 or ?52 from Micrometals, the inductance “swing”
with dc bias must be taken into account ? inductance will
decrease as the dc input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
dILo dt + D VLo Lo
(16)
http://onsemi.com
26
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