参数资料
| 型号： | NCP5331FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 28/36页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH W/DRVRS 32-LQFP |
| 产品变化通告： | Product Obsolescence 05/Oct/2010 |
| 标准包装： | 1 |
| 应用： | 控制器，AMD Athlon? |
| 输入电压： | 9 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5331FTR2GOSCT |
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NCP5331
For TO?220 and TO?263 packages, standard FR?4
copper clad circuit boards will have approximate thermal
resistances ( q SA ) as shown in the following table.
determine the V FB bias current. Usually, the no?load voltage
increase is specified in the design guide for the processor
that is available from the manufacturer. The V FB bias current
is determined by the value of the resistor from R OSC to
Pad Size
(in 2 /mm 2 )
Single?Sided
1 oz. Copper
ground (see Figure TBD for a graph of IBIAS VFB versus
R OSC ). The value of R F1 can then be calculated.
0.5/323
60?65 ° C/W
RF1 + D VNO?LOAD IBIASVFB
(29)
0.75/484
1.0/645
1.5/968
2.0/1290
2.5/1612
55?60 ° C/W
50?55 ° C/W
45?50 ° C/W
38?42 ° C/W
33?37 ° C/W
Resistor R DRP is connected between the V DRP and the
V FB pins. At no?load, the V DRP and the V FB pins will both
be at the DAC voltage so this resistor will conduct zero
current. However, at full?load, the voltage at the V DRP pin
will increase proportional to the output inductor ’s current
while V FB will still be regulated to the DAC voltage. Current
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow, maximum
input voltage, maximum loading, and component variations
(i.e., worst case MOSFET R DS(on) ). Also, the inductors and
capacitors share the MOSFET’s heatsinks and will add heat
and raise the temperature of the circuit board and MOSFET.
For any new design, its advisable to have as much heatsink
area as possible ? all too often new designs are found to be
too hot and require redesign to add heatsinking.
6. Adaptive Voltage Positioning
There are two resistors that determine the Adaptive
Voltage Positioning, R F1 and R DRP . R F1 establishes the
will be conducted from V DRP to V FB by R DRP . This current
will be large enough to supply the V FB bias current and cause
a voltage drop from V FB to V CORE across R F1 ? the
converter ’s output voltage will be reduced. This condition is
shown in Figure 34.
To determine the value of R DRP the designer must specify
the full?load voltage reduction from the VID (DAC) setting
( D V CORE,FULL?LOAD ) and predict the voltage increase at
the V DRP pin at full?load. Usually, the full?load voltage
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the
voltage increase at the V DRP pin at full?load ( D V DRP ), the
designer must consider the output inductor ’s resistance
(R L ), the PCB trace resistance between the current sense
points (R PCB ), and the controller IC’s gain from the current
sense to the V DRP pin (G VDRP ).
no?load “high” voltage position and R DRP determines the
full?load “droop” voltage.
D VDRP + IO,MAX @ (RL ) RPCB) @ GVDRP
(30)
D VDRP (31)
(IBIASVFB ) D VCORE,FULL?LOAD RF1)
Resistor R F1 is connected between V CORE and the V FB
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V FB pin and develop a voltage
drop from V CORE to the V FB pin. Because the error amplifier
regulates V FB to the DAC setting, the output voltage,
V CORE , will be higher by the amount IBIAS VFB ? R F1 . This
condition is shown in Figure 33.
To calculate R F1 the designer must specify the no?load
voltage increase above the VID setting ( D V NO?LOAD ) and
The value of R DRP can then be calculated.
RDRP +
D V CORE,FULL?LOAD is the full?load voltage reduction
from the VID (DAC) setting. D V CORE,FULL?LOAD is not the
voltage change from the no?load AVP setting.
L1
0A
R S1
C S1
CS1
+
?
G VDRP
Σ
COMP
Error
Amp
+?
VID Setting
IBIAS VFB
R S2
CS2
+
?
R DRP
V DRP = VID
V FB = VID
R F1
V CORE
L2
0A
C S2
CS REF
G VDRP
I DRP = 0
I FBK = IBIAS VFB
V CORE = VID + IBIAS VFB w R F1
Figure 33. AVP Circuitry at No?Load
http://onsemi.com
28
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