参数资料
| 型号： | NCP5331FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 31/36页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH W/DRVRS 32-LQFP |
| 产品变化通告： | Product Obsolescence 05/Oct/2010 |
| 标准包装： | 1 |
| 应用： | 控制器，AMD Athlon? |
| 输入电压： | 9 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5331FTR2GOSCT |
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NCP5331
the inductor ’s resistance increase due to current heating and
G CSA
is the Current Sense Amplifier Gain
VILIM + (IOUT,LIM ) D ILo 2) @ R @ GILIM
ambient temperature rise. Also, depending on the current
sense points, the circuit board may add additional resistance.
In general, the temperature coefficient of copper is +0.393%
per ° C. If using a current sense resistor (R SENSE ), the I LIM
pin voltage should be set based on the maximum value of the
sense resistor. To set the level of the I LIM pin,
(34)
(nominally 2.0 V/V),
Startup Offset is typically 0.60V.
12. Power Good Delay Time
The power good timer sets the delay time between when
V CORE exceeds the C PGD comparator ’s threshold voltage
and when PGD will actually transition high. The PGD delay
time can be calculated from
where
I OUT,LIM is the current limit threshold of the converter,
D I Lo /2 is half the inductor ripple current,
tPGD + CPGD @ (PGDTHRESH * PGDMIN) IPGD
+ CPGD @ (3.0 V * 0.25V) IPGD
(37)
tOVC + COVC @ (OVCTHRESH * OVCMIN) IOVC
R is either (R LMAX + R PCB ) or R SENSE ,
G ILIM is the current sense to I LIM gain.
For the overcurrent protection to work properly, the
current sense time constant (RC) should be slightly larger
than the RL time constant. If the RC time constant is too fast,
during step load changes the sensed current waveform will
appear larger than the actual inductor current and will
probably trip the current limit at a lower level than expected.
10. Overcurrent Timer
The overcurrent timer sets the time the converter will
allow hiccup mode operation. Given the capacitance from
the C OVC pin to GND, the nominal overcurrent time (t OVC )
can be calculated from the following equation.
(35)
+ COVC @ (3.0 V * 0.25 V) 5.0 m A
+ COVC @ 5.5 105
where
OVC THRESH is the overcurrent timer ’s shutdown
where
PGD THRESH is the PGD comparator ’s threshold
voltage, nominally 3 V,
PGD MIN is the PGD timer ’s starting voltage,
nominally 0.25 V,
I PGD is the charge current supplied to the
capacitor at the C PGD pin. This current
is a function of the R OSC resistor
according to I PGD = 0.52 V/R OSC .
Design Example
Typical Design Requirements:
V IN = 12.0 Vdc
V CORE = 1.20 Vdc (nominal)
V OUT,RIPPLE < 20 mV PP max
VID Range: 0.800 Vdc ? 1.550 Vdc
I O,MAX = 52 A at full?load
I OUT,LIM = 72 Adc
dI IN /dt = 0.50 A/ m s max
OVC MIN
I OVC
voltage, nominally 3 V,
is the overcurrent timer ’s starting
voltage, nominally 0.25 V,
is the charge current supplied to the
f SW = 200 kHz
η = 80% min at full?load
T A,MAX = 55 ° C
T J,MAX = 120 ° C
capacitor at the C OVC pin, nominally
5 m A.
11. Soft Start Time
The Soft Start time (t SS ) can be calculated from
tSS + (VCOMP * RC1 @ ICOMP) @ CC2 ICOMP (36)
where
VCOMP + VCORE @ 0 A ) Channel_Startup_Offset
) Int_Ramp ) GCSA @ Ext_Ramp 2
Ext_Ramp + D @ (VIN * VCORE) (RCSx @ CCSx @ fSW)
Int_Ramp + 125 mV @ D 0.50
t SS = 6.0 ms (Soft Start time)
t OVC = 120 ms (Overcurrent time)
t PGD = 6.0 ms (PGD Delay time)
D V CORE at no?load (static) =
?25 mV from VID setting = 1.225 Vdc
D V CORE at full?load (static) =
–37 mV from VID setting = 1.163 Vdc
D V CORE transient loading from 3.0 A to 25 A =
?50 mV from VID setting = 1.150 Vdc
1. Output Capacitor Selection
First, choose a low?cost, low?ESR output capacitor such
as the Rubycon 16MBZ1000M10X16: 16 V, 1000 m F,
2.55 A RMS , 19 m W , 10 × 16 mm. Calculate the minimum
number of output capacitors.
D IO,MAX
D VO,MAX
I COMP
Int_Ramp
Ext_Ramp
is the COMP source current from the
data sheet,
is the internal ramp value at the
corresponding duty cycle,
is the peak?to?peak external
NOUT,MIN + ESR per capacitor @
+ 19 m W @ 22 A (1.225 V * 1.150 V)
+ 5.6 or 6 capacitors minimum (6000 m F)
(1)
steady?state ramp at 0 A,
http://onsemi.com
31
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